CORDIC Brings Math To FPGA Designs

We are always excited when we see [Hamster] post an FPGA project, because it is usually something good. His latest post doesn’t disappoint and shows how he uses the CORDIC algorithm to generate very precise sine and cosine waves in VHDL. CORDIC (Coordinate Rotation Digital Computer; sometimes known as Volder’s algorithm) is a standard way to compute hyperbolic and trigonometric functions. What’s nice is that the algorithm only requires addition, subtraction, bit shifts, and a lookup table with an entry for each bit of precision you want. Of course, if you have addition and negative numbers, you already have subtraction. This is perfect for simple CPUs and FPGAs.

[Hamster] not only has the VHDL code but also provides a C version if you find that easier to read. In either case, the angle is scaled so that 360 degrees is a full 24-bit word to allow the most precision. Although it is common to compute the result in a loop, with the FPGA, you can do all the math in parallel and generate a new sample on each clock cycle.

It is actually impressive how short the VHDL code is. VHDL is fairly verbose, too, so we imagine a Verilog translation would be very svelte. Oddly, while OpenCores has a few CORDIC projects, we didn’t see any written in Verilog. We did however find a few on GitHub, including a fairly complex one from [ZipCPU].

The history of CORDIC is interesting, too. [Jack Volder] worked for a defense contractor and had the task to replace the analog resolver on a B-58 bomber’s navigation computer with something both more accurate and real time. He conceived CORDIC in 1956 based on formulae found in the CRC Handbook but left the company before they built devices that used them. In 1965, [Volder] build Athena, a desktop calculator using CORDIC but Hewlett-Packard didn’t bite on it, although it did influence early HP machines.

10 thoughts on “CORDIC Brings Math To FPGA Designs

    1. I don’t like being the citation needed guy, but do you have a ref for that? I thought the Sinclair Scientific used much dirtier approximations, some of which were only accurate to a few decimal places.

  1. Once I’ve used CORDIC, too, for this project:
    http://www.frank-buss.de/SignalGenerator/index.html
    This is the source code:
    http://www.frank-buss.de/SignalGenerator/vhdl/cordic.vhd
    Unlike the version from Hamster, in my version the individual steps are executed each at one clock cycle. Hamster synthesized all steps in one loop. This could be a problem for high clock rates.
    This is the C program to generate the table and to measure the error:
    http://www.frank-buss.de/SignalGenerator/software/table/table.c
    BTW, for modern FPGAs and CPUs it doesn’t make sense to use CORDIC, because they have hardwired multiplication.

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