Weird CPU

How many instructions does [agp.cooper’s] computer have? Just one. How many strip boards does it use? Apparently, 41 five 41-track boards. While being one shy from the answer to life, it is still a lot of boards for a single instruction. The high board count is due to the use of 1970’s vintage ICs including TTL parts, 2114 RAM chips, and 74S571 PROMs.

There are several different architectures for single instruction computers and [agp’s] uses what is technically at TTA (transfer-triggered architecture). That is, the one instruction is a move and the destination or source of the move determines the operation. For example, the Wierd CPU (that’s the name of it) has a P and Q register. If you load those registers and then the ADD register will contain the sum of the two numbers.

There are not many  functional units (like ADD), either. There’s a few jumps, some I/O, and you can do a NAND or an ADD operation. We don’t blame him for being economical with such a large number of boards and parts. However, if you make the leap to FPGA, you can build a much more capable one instruction machine. However, we’ve covered many other one instruction wonders, including the breadboardable DUO Compact and the SUBLEQ-OISC.


24 thoughts on “Weird CPU

  1. It uses FIVE, 41 track, strip-boards.

    It is an interesting project, and well documented too. I like how cleanly the boards are used with the tracks acting as busses, much easier to get your head around. I guess it can be expanded to any number of boards for additional locations/functions?
    A diode ROM board for a universal (addressable) logical function would be nice, to have more than just NAND as an option.

  2. Quote from this page: “How many strip boards does it use? Apparently, 41”
    Quote from project page: “It was built using 41 track strip-board”

    There are actually 5 boards excluding the PROM programmer.

    The 41 strips – stripboard is getting hard to get now. Most of what I see has 36 strips (34 drilled).

  3. One more of these retro style computers and I will pushed over the edge of insanity and start building that card rack / back-plane computer that I never built as a kid.

    I looked at all those well formed wire links and it reminded me of how we used to take so much care with designs that every link was perfect and every component was aligned perfectly. I was tempted for a while then I remembered how hard and time consuming it was and how easy it is to make circuit boards today.

    But still, I have 100 odd 5 Volt tolerant CPLD’s for glue and lots of old 5 Volt chips like FLASH, SRAM. CPU and all the header connectors and I have card guides bookmarked on ebay so I am just a smidgen away from the insanity of actually building it.

    The simplicity of these projects is wonderful but those old prototyping techniques were all so time consuming. I even re-visited wire-wrap and that seems to have fallen in a heap as it is so time consuming.

      1. It will have to sit on the back burner longer or I would have to finish or abandon two other projects first. I am adding a hard drive to another retro computer and I hope to finish the bulk of that soon.

    1. A CPLD based CPU sounds decidedly awesome dude. Just so you know, I myself am building my own 6502 based computer, so let me be the one to push you over the edge and get you working on your own machine. XD

      1. LOL, I was only going to use the CPLD as glue logic. The ones I have heaps of, are only 36 registers. If I were to make a CPU out of them, then the PCB would look like it had a cockroach (IC) infestation!!! It’s probably doable for simple CPU though co I can chain the JTAG.

        Must NOT make CPU from CPLD.
        Must NOT make CPU from CPLD. DOH!

    1. There is an old software saying:

      1. All software has bugs.
      2. All software can be made smaller.

      3. All programs can be reduced to one line of code that doesn’t work right.

        1. “Subtract, branch if negative” is a Turing-complete one-instruction CPU. OISC computing, it’s a thing. Not a thing that anyone actually does for practical reasons, but still.

          This is “transport triggered architecture”. Which is really cheating in my mind. It’s using addresses as instructions, so really addresses are just an unusual method of instruction coding. Not really one instruction!

          1. That’s in the small print when you meet the genie, everyone knows that. The fact that “subtract, branch if negative” can actually do all mathematics and computing, is a wonderful bit of logic. Transport-triggered, like this, aren’t beautiful like that. It’s just hiding the instructions in the address bits instead of the instruction opcodes. Which this doesn’t have, cos there’s only one. So essentially some of the address bits become an opcode. You could have addresses to do any op you wanted, you could probably implement a Pentium with a bit of bit-twisting. This thing has more than one operation, even if it’s disguised as not an “instruction”.

            Know what I mean? It’s not as logically beautiful.

          2. I agree with Greenaum, but TTA also has a neat feature – the ease of adding and removing instructions from the architecture. You could even think of something like having flexible instruction set for different applications.

          3. Yeah but there’s other, more efficient, ways of having an updatable instruction set, like microcode for one. Some people have implemented those too, on breadboard or simple PCBs, you use an EPROM to send out the various control signals for your CPU’s logical parts, and a simple counter as a sequencer, to count through the EPROM. I suppose if you made it SRAM instead of EPROM you’d have a dynamically updateable CPU.

            Still, yes, it is nice how TTA does abstract the functional bits into addresses like that. And I’m certainly not saying this isn’t a cool piece of hardware, I’m sure it’s fun and interesting for the guy to make. And it covers the ground between software and silicon well, which is something a lot of software people don’t really understand. I’ve just got a very specific and unusual beef with TTA as a “OISC”, cos it isn’t one.

          4. What do you get if you link into a loop a series of RAM modules where the data lines of one module can act as inputs to the address lines of another?

          5. Also… there was a byte-copying OISC machine on HAD a few weeks ago, that worked, I think, with an instruction with 2 operands plus an address to jump to. Worked by lots of self-modifying code, changing around the jump addresses. That had no instructions at all! Didn’t transport-trigger anything, just copied data. Called a byte-byte-jump machine I think.

            I think even writing a Brainfuck compiler for that would be an effort.

  4. I always love this kind of project, makes me wish I was around for the early days of hardware hacking. It gives a sense of the level of abstraction we deal with today. This is art, as much as it is science. The layout and structure of Weird CPU is especially visually appealing.

    1. It’s a common misconception that you can’t hack on this stuff nowadays :) With the online parts resources we’ve got nowadays, pretty much anyone with a little spare cash can pick up enough parts to build something in the spirit of 70’s or 80’s homebrew computers.

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