Homebrew Network Card With No CPU

A modern normal network card will have onboard an Ethernet controller which, of course, is a pre-programmed microcontroller. Not only does it do the things required to keep a computer on the network, it can even save the primary CPU from having to do certain common tasks required for communicating. But not [Ivan’s]. His homebrew computer — comprised of 7 colorful PCBs — now has an eighth card. You guessed it. That card connects to 10BASE-T Ethernet.

There’s not a microcontroller in sight, although there are RAM chips. Everything else is logic gates, flip flops, and counters. There are a few other function chips, but nothing too large. Does it work? Yes. Is it fast? Um…well, no.

The complete computer.

He can ping others on the network with an 85 ms round trip and serve web pages from his homebrew computer at about 2.6 kB/s. But speed wasn’t the goal here and the end result is quite impressive. He even ported a C compiler to his CPU so he could compile uIP, a networking stack, avoiding the problems of writing his own from scratch.

Some compromises had to be made. The host computer has to do things you normally expect a network card to do. The MTU is 1024 bytes (instead of the more common 1500 bytes, but TCP/IP is made to expect different MTU sizes, which used to be more common when more network interfaces looked like this one).

Even on an FPGA, these days, you are more likely to grab some “IP” to do your Ethernet controller. Rolling your own from general logic is amazing, and — honestly — the design is simpler than we would have guessed. If you check out [Ivan]’s blog, you can find articles on the CPU design, its ALU, and even a VGA video card all from discrete logic. The whole design, including the network card is up on GitHub.

We love the idea of building a whole computer system soup to nuts. We wish we had the time. If you need a refresher on what’s really happening with Ethernet, our [Arya Voronova] can help.

Only 8 Chips Make A CPU

We’re no stranger to homemade CPUs on these pages, but we think that [Jiri Stepanovsky]’s 16-bit serial CPU might be a little special. Why? It has an astonishingly low chip count, with only 8 ICs in total. How on earth does he do it?

While a traditional TTL CPU has a relatively high chip count due to a parallel data bus, registers, and discrete ALU, this one takes a few shortcuts by opting for a one-bit serial bus with serial memory chips and an EPROM serving as a look-up-table ALU. Perhaps the most interesting result of this architecture is that it also allows the CPU to dispense with registers, like the Texas Instruments 16-bit chips back in the day. They all live in memory. You can see it below the break in action, streaming a video to a Nokia-style LCD.

Such a CPU would indeed have been unlikely to have been made back in the day due to the prohibitive cost of buying and programming such a large EPROM. However, old computers like the EDSAC also used a serial data path and mercury delay line memory to manage complexity. But for a solid-state CPU in 2023, we think the design is innovative. We think it would be challenging to reduce the chip count further — and no, we’re not counting designs that use a microcontroller to replicate a block of circuitry; that’s cheating — but we’re sure that somewhere there’s a designer with ideas for slimming the design further.

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SCAMP runs SCAMP/os

Homebrew 16 Bit Computer Reinvents All The Wheels

Building your own computer has many possible paths. One can fabricate their own Z80 or MOS 6502 computers and then run a period correct OS. Or a person could start from scratch as [James Stanley] did. [James] has invented a completely unique computer and CPU he calls SCAMP. SCAMP runs a custom OS called SCAMP/os which you can check out in the video below the break.

[James] describes the CPU and computer as purposefully primitive. Built out of discrete 74xx series logic chips, it runs at a fast-enough-for-homebrew 1 MHz. Plus, it has a lot of blinking lights that can’t help but remind us of the original Imsai 8080. But instead of a panel of switches for programming, the SCAMP/os boots to a shell, which is presented through a serial terminal. Programs are written in a bespoke language with its own compiler. The OS is described as a having a Unix-like feel with CP/M-like functionality. That’s quite a combination!

What we love most about the build, other than its clean looks and blinkenlights, is the amount of work that [James] has put into documenting the build both on his blog and on Github, where the source code and design is available. There’s also an open invitation for contributors to help advance the project. We’re sure he’ll get there, one bit at a time.

While [James] is using a Compact Flash card for storage currently we can’t help but wonder if a Cassette Tape storage system might be a worthwhile future upgrade.

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The Logic Chip RISC-V Project Reboots

The RISC-V architecture is inexorably inching from its theoretical origins towards the mainstream, as what could once only be done on an exotic FPGA can now be seen in a few microcontrollers as well as some much more powerful processors. It’s exciting because it offers us the prospect of fully open-source hardware on which to run our open-source operating systems, but it’s more than that. RISC-V isn’t a particular processor core so much as a specification that can be implemented at any of a number of levels, and in its simplest form can even be made real using 74 logic chips. This was the aim of [Robert Baruch]’s LMARV-1 that caused a stir a year or two ago but then went on something of a hiatus. We’re pleased to note that he’s posted a video announcing a recommencement of the project, along with a significant redesign.

We’ve placed the video below the break, and it’s much more than a simple project announcement. Instead, it’s an in-depth explanation of the design decisions and the physical architecture of the processor. It amounts to a primer on processor design, and though it’s a long watch we’d say you won’t be disappointed if your interests lie in that direction.

We first covered the LMARV-1 back in early 2018, so we’re glad to see it back in progress and we look forward to seeing its continued progress.

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A Breadboard Block For 8-Bit CPUs

Breadboard CPUs are a fantastic learning experience and require serious dedication and patience. Occasionally, CPU builders eschew their breadboards and fab their design onto a PCB. But this takes away the flexibility and some of the opportunity for learning that breadboard CPUs offer. [c0pperdragon] was doing the same sort of repetitive wiring from project to project as most 8-bit breadboard CPUs use memory, a bus, an IO controller, ROM, and a few other passive components.

Taking a compromise approach, [c0pperdragon] built a PCB that can be used as a building block in his custom CPUs which they have titled “ByteMachine”. A single row of 34 pins offer power, clock, reset, 19 address bus lines, 8 data bus lines, and a ROM selector. This means that the CPUs can fit on a single breadboard and can run faster as the impedance of the breadboard has less effect on the circuit. With 512 KB of RAM and 512 KB of ROM, in a ZIF socket for easy reprogramming, ByteMachine has plenty of space.

One drawback is the lack of IO. There is no dedicated address space as this would require decoding logic between the RAM and the CPU. [C0pperdragon] added a simple 8-bit output register provided by a 74-series logic IC. The data is displayed on 8 red LEDs and can be accessed via pins. Input is accomplished in a similar way with just 8 bits of digital input provided.

[C0pperdragon] has built the 65C02, 65C816Z84C00, and the i8088 with the ByteMachine. Each was documented with incredible schematics, pictures, and test programs on GitHub. Next time you’re looking to build a CPU on a breadboard, maybe start with a ByteMachine. In some ways, it might improve your learning experience as it makes the incredible mass of wires we’ve seen on other projects a tad more manageable.

Thanks [Reinhard Grafl] for sending this one in!

64-bit And A Display: Minecraft Computers 10 Years Later

Some people build their own computer to play games, while others play games to build their own computer. Minecraft is the prime candidate for the latter, and while you can certainly arrange the blocks to make them look like a computer, we’re of course talking about replicating the actual functionality of a CPU or parts thereof, and/or external components within the game. Many such creations have spawned in the decade since the first Minecraft-built ALU surfaced, and [Rockfarmor] built a 64-bit specimen to add to that list — and made a video to showcase it.

Instead of emulating a common architecture, [Rockfarmor] went for a more home-made approach, and re-used the architecture from an old school assignment (in Swedish) as basis. The result is a simple yet fully functional 64-bit CPU with 32 registers, 32kB main memory and a separate 16kB stack. The instruction set mostly contains ALU and branching operations, but also a few special opcodes to control an additional 64×64 pixel blocks, 64-color display — including drawing circles, lines, and color fills.

More details on the architecture can be found in its documentation and in an older video (with subpar audio circumstances unfortunately). An additional time-lapse video of the initial build is also available, and you will find all of them after break. To simplify development, [Rockfarmor] also wrote a desktop app to program the computer in assembly and upload it straight to the Minecraft version.

As with all computers built in Minecraft, the driving force is redstone, which essentially allows circuit design within the game, and [Rockfarmor]’s is no difference here. He also uses command blocks to avoid the laboriously and slow “wiring” required otherwise, turning it more into a “wireless redstone” circuit.

No doubt, purists will consider this cheating, but another angle would be to see it as Moore’s Law applied to Minecraft computers, considering the computer’s size and speed compared to the first Minecraft ALU. Or maybe as the equivalent of microcode in real-world CPUs? Or then, maybe we should just accept and embrace different options and preferences.

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An 8-Bit Transport Triggered Architecture CPU In TTL

When we are introduced to the internals of a microprocessor, it is most likely that we will be shown something like one of the first generation of 8-bit CPUs from the 1970s. There will be the familiar group of registers and counters, an arithmetic and logic unit (ALU), and an instruction decoder with associated control logic. A complex instruction set causes the decoder to marshal registers and ALU to perform all the various functions in the right order. CPUs may have moved on in many ways since the 1970s, but the block diagram of an 8080 or similar still provides a basic grounding for the beginner.

So when we tell you about another home-made CPU using TTL logic chips, you might expect it to follow this well-worn path. Fortunately though the hardware hacking community is always capable of springing surprises upon us, and [Szoftveres] has done just that with his design. It’s a one-instruction-set machine following a transport triggered architecture, and that means it deviates sharply from the conventional architecture described above. Each instruction is a move between the different physical functions of the processor, and computation is achieved by the physical functions working on the data as it is moved into them and presenting the result on their outputs ready to be moved elsewhere. The result is a computer that is in its own way beautifully simple, though at the expense of some inflexibility and lack of some hardware functions we take for granted in more conventional processors.

This machine has been built on a piece of stripboard, and has an accompanying board with display, keypad, and a modem. There is a small board based upon an ATmega8 microcontroller which performs the function of fast program loading, and can be removed once the code is loaded. Software can be written in a C-like language anc compiled using the compiler in his GitHub repository, and he has produced a YouTube video of the machine in operation. This project is well worth reading through in-depth, for its introduction to this slightly unusual architecture.

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