Ice, Ice, Radio Uses FPGA

Building a software defined radio (SDR) involves many trades offs. But one of the most fundamental is should you use an FPGA or a CPU to do the processing. Of course, if you are piping data to a PC, the answer is probably a CPU. But if you are doing the whole system, it is a vexing choice. The FPGA can handle lots of data all at one time but is somewhat more difficult to develop and modify. CPUs using software are flexible–especially for coding user interfaces, networking connections, and the like) but don’t always have enough horsepower to cope with signal processing tasks (and, yes, it depends on the CPU).

[Eric Brombaugh] sidestepped that trade off. He used a board with both an ARM processor and an ICE FPGA at the heart of his SDR design. He uses three custom boards: one is the CPU/FPGA board, another is a 10-bit converter that can sample at 40 MSPS (sufficient to decode to 20 MHz), and an I2S DAC to produce audio. Each board has its own page linked from the main project.

You can find the C and Verilog sources for the device on GitHub. [Eric] also has a great block diagram and description of how everything works available. So far, the device can handle AM, synchronous AM, narrow-band FM, as well as upper and lower sideband (or both at once). It can also send raw IQ signals directly out for further processing.

Oddly enough, we haven’t talked about [Eric’s] design before, but a picture of it appeared in a past post about (among other things) the PMOD connector system (since the DAC uses PMOD as its interface). [Eric’s] device handles about 20 kHz of bandwidth at a time. If you want something more (also with an FPGA), check out FreeSRP.

24 thoughts on “Ice, Ice, Radio Uses FPGA

  1. Nice work.

    Some constructive advise: You could improve your front-end immensely by doing a better job at an anti-alias filter in front of the ADC. 50-ohm followed by 20pF is not good enough (only about 250MHz 3dB cutoff with) Nyquist low pass should be steep filter attenuating all frequencies above 10 Mhz for 20 MHz sampling rate (unless you are doing band-pass + under sampling) . You probably also want to design the filter to be linear phase. .. especially with 20 MHz bandwidth.

    1. The RXADC board was designed to be as broadband as possible in order to allow experimenting with IF undersampling. I have a selection of filters that I insert prior to the driver amp to support different bandwidths which are described on a separate page at my site:

      If I were trying to process the entire 20MHz of available bandwidth then linear phase might be helpful, but since the iceRadio design downconverts and decimates to a fairly narrow bandwidth that’s not so important in this case.

    1. That goes to show that you, dear anonymous, have very superficial knowledge.

      a) 40MS/s inside an SDR receiver doesn’t tell us whether he’s doing bandpass or complex baseband sampling. With that number, we know he’s doing real-valued sampling

      b) just because your ADC covers a bandwidth of x Hz doesn’t meant that the signal fed to that is also that close to that bandwidth – for example, you could have a filter that is 16 MHz wide and has a 4 MHz wide transition between pass- and stop band, and these 4 MHz would then overlay with the aliases “from the other end” in the upper and lower 2 MHz. So this is the author inherently claiming he has a system with a nearly perfect filter (which he hasn’t).

      1. My discussion of the front end processing on this project is deliberately ambiguous because I have used several different types. For the simplest case I have a 5th-order LC low pass filter with ~20MHz corner frequency which won’t prevent aliasing up in the 15-20MHz range but is fine for most SW and amateur bands below 20m. I also have a number of different VHF downconverter designs that I’ve tried, some of which use IF frequencies above 20MHz and require bandpass undersampling.

        The main thing to take away from this is that up to 20MHz bandwidth is possible under ideal (and mostly unrealistic) conditions but I’m not claiming to have actually achieved that with the hardware on my bench.

    2. I don’t think it is pretensions at all. [Al Williams] has demonstrated a skill set that suggests that he clearly understands Nyquist frequency. Perhaps you meant condescending or demeaning, in which case I would still disagree because there is a broad readership here and there would be those who have not previously come across Nyquist frequency.

      It’s always better to provide more information than insufficient information.

    1. DAB+ is not really what this is designed for. This is mainly an HF narrowband receiver, mainly focused on analog modulations. DAB+ is a compressed digital waveform broadcast in the 88-108 VHF FM band.

  2. ebrombaugh: The Blinkenlights Trolls are out in full force on this thread. Awesome job! The fact you could squeeze that much into a Ice5LP4K is a borderline miracle.

    1. Thanks! I did some more tweaking on the design and boosted it up to 14-bit 50MSPS for the ADC input and it works pretty well. I’ve still got some more things I want to try with it, but these FPGAs are pretty capable if you just manage the resources carefully.

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