The 2019 Hackaday Superconference kicked off with a marvelous, and marvelously geeky, keynote talk on the subject of RISC-V by Dr. Megan Wachs. She is VP of Engineering at SiFive, a company that makes RISC-V processors in silicon, but the talk is a much more general introduction to the RISC-V open instruction-set architecture (ISA) and why you’d care. The short answer to the latter is the same reason you care about any other open standard: it promotes interoperability, reusable toolchains, and will result in us all having access to better and faster CPUs.
The video is embedded below, and it’s absolutely worth a watch. Unfortunately, The video is missing the first few minutes, you can follow along through her slides (PDF) and read through our brief recap below of what fell down the video hole.
Dr. Wachs starts off the talk by defining an ISA: it’s essentially the dictionary that describes all of the words that a computer speaks. When you write, for instance,
a + b = c in your favorite programming language, a compiler turns this into assembly code (
add a5, a5, a4), which then gets turned into the binary bits of the CPU’s machine code. The ISA covers the assembly and machine languages, defining all of the possible operations, what arguments they take, and in which registers or farther memory locations they store their results.
A common ISA is a big deal. An x86 and an ARM CPU add numbers together in entirely different ways, and this means that you need different compilers, assemblers, and debuggers to process your code depending on which chip you’re targeting. But it spreads out from there. Hardware emulators, visualizers, documentation, and everything else in the low-level ecosystem needs to be customized to the CPU’s architecture. If you think of all of the proprietary ISAs that have gone before, competed with each other, and are now gone (VAX, Itanium, SPARC, and many more), a lot of this effort is lost. And looking into the future, as more and more components get integrated into systems-on-chip (SoCs), needing to wrangle a dozen ISAs just to program a system is not out of the question. Dr. Wachs mentioned the NVIDIA Tegra SoC, with multiple DSP units for sound and audio, a video encoder, two CPUs, a graphics processor, display drivers, a USB peripheral, etc. on board, each with unique software stacks.
RISC-V (“risk five”), originally a student project at Berkeley, solves this with essentially the simplest possible, open, ISA design. A stripped-down RISC-V CPU is something that can be taught to undergrads, yet it’s also modular enough that you can include hardware multipliers and other optimizations if you feel like it. As long as you stick to the ISA standard, you’ll have the compliers, debuggers, and the rest of the software ecosystem ready for your design.
And with a number of RISC-V FPGA cores available, this isn’t just an academic proposition. You, yes you, could be playing around with actual CPU designs in a weekend, and for not very much financial outlay. Driving this point home, the badge that everyone in Dr. Wachs’ audience had hanging around their necks had not just one but two RISC-V CPUs running inside it. We’ve seen smaller and less expensive FPGA development boards that’ll fit the bill too. Sure, there’s a learning curve, but it has never been easier to climb it.
Open hardware designs are important for security, low-power applications, cutting costs, research, and generally hacking around. The last third of Dr. Wachs’ talk is dedicated to ways that you might want to use, tweak, and build on the RISC-V environment. Open standards make things smoother for large companies too, of course, and that means that you’re going to see more and more microcontrollers and even desktop CPUs running on RISC-V: open-standard hardware to go with your open-source software. But if you want to dive deeper, the most benefit from RISC-V is actually going to accrue to the hackers. Where playing around with CPU designs used to be impossible for the little guy or gal, it’s now within reach. Watch the Supercon Keynote and see if you don’t get inspired.
Megan Wachs Interview at Supercon
After her keynote, Dr. Wachs spent some time in the badge hacking area discussing the work she’s been doing at SiFive in getting from an ISA to producing chips: