A process design kit (PDK) is a by now fairly standard part of any transformation of a new chip design into silicon. A PDK describes how a design maps to a foundry’s tools, which itself are described by a DRM, or design rule manual. The FOSSi foundation now reports on a new, open PDK project launched by Google and SkyWater Technology. Although the OpenPDK project has been around for a while, it is a closed and highly proprietary system, aimed at manufacturers and foundries.
The SkyWater Open Source PDK on Github is listed as a collaboration between Google and SkyWater Technology Foundry to provide a fully open source PDK and related sources. This so that one can create manufacturable designs at the SkyWater foundry, that target the 130 nm node. Open tools here should mean a far lower cost of entry than is usually the case.
Although a quite old process node at this point (~19 years), it should nevertheless still be quite useful for a range of applications, especially those that merge digital and analog circuitry. SkyWater lists their SKY130 node technology stack as:
- Support for internal 1.8V with 5.0V I/Os (operable at 2.5V)
- 1 level of local interconnect
- 5 levels of metal
- Inductor-capable
- High sheet rho poly resistor
- Optional MiM capacitors
- Includes SONOS shrunken cell
- Supports 10V regulated supply
- HV extended-drain NMOS and PMOS
It should be noted that use of this open source PDK is deemed experimental at this point in time, and should not be used for any commercial or otherwise sensitive applications.
Header image: Peellden/ CC BY-SA 3.0
Damn 130, thought there were academic tools around that could do 22… mind you that’s not so much a kit/IDE, but this tool for that, etc.
You can do a lot with 130 nm, especially with Analog and RF. There is a general obsession with the latest tech nodes because that is the popular message that goes around. Now that Moore’s law has slowed down, there is a scope for easier access to semiconductor fabrication leading to innovative architectures rather than relentless pursuit of smaller transistors. In many ways, 130 nm is much better for a general use case since (as you mention), tech nodes like 22 nm require specialized tools, tons more constraints and checks, double patterned metal etc. Not to mention the DRCs. The number of IC layout DRC rules go up exponentially with tech node shrinking.
6502 processor was 8000 nm, and 21 mm^2. 65C02 was 3000 nm and 6 mm^2. Pentium III was 130 nm and 91 mm^2.
https://en.wikipedia.org/wiki/Transistor_count
I guess this means we can recreate the SID chips with ease. And no need for 12V anymore. And probably like 1 mm^2, if it was possible to have 40 pins connected to such a small die. ;)
I have been DREAMING for a new run of SID chips for years now. Given the difference in nm scale between the original MOS fab and the SkyWalker foundry you could probably throw in Stereo SIDs, and the VIC-II chip as well. Heck, you could thrown in a couple of ADCs and a HDMI block for a chip that can do modern display/audio output on a C64
Just a github page, with some very bare-bones “documentation” a code of conduct, and not much else.
Call me when they have synthesis models, .lib files, gds2 files, lef files, def files, verilog simulation models, timing models, ATPG models, scan insertion models, SPICE models, DRC/ERC/LVS rule decks, and all the other cell views required for synthesis, test, and rtl to GDS2.
Wow! Did not know Mr. Gates is hardware design engineer 😂😂
Some of those are your part of the design not the PDK. Call me when it’s ready.
did you clone recursively ?
Interesting project. Not much to work with yet, but it has just started up. It looks to belong to the “check this bookmark in a month” category. Back in college, I messed with an open-source ASIC design tool that only supported a couple of metal layers, but I’ll be damned if I can remember the name of it.
Maybe you’re thinking of MAGIC?
So this means somone could now replicate SID or VIC chips for C64? or ULA for ZX Spectrum?
For the ULA there are RTL models available, for the other two… Maybe having the SID masks would help, the VIC has been quite successfully re-implemented, too.
mhm if only we had die shots… http://mail.lipsia.de/~enigma/neu/6581.html :)
Maybe a silicon implementation of the FPGA-based ZX Spectrum Next?
What’s wrong with the FPGA implementation? That is silicon based as well! Unless you see a need for 100’s of thousands of units volume (or have some other kind of unique requirement, which given that you have it in an FPGA wouldn’t appear to be the case), I doubt an ASIC implementation would be financially viable vis a vis the FPGA.
I cant wait for the day when you can order 10 asics (10x10mm) for 100$
like you can order 10 pcbs (10x10cm) for 10$ today
That would be absolutely amazing even if its 130nm!!!!!!!!!
Contextual reminder that the Pentium III was 130nm family, so there’s plenty of Oomph to be found, especially if you allow for more lenient requirements in some ways
There’s quite a lot to unpack in this…I think somewhere along the way there has been some confusing about OpenPDK and Open Sourced PDK, and how PDK’s and IP libraries are licensed in the first place.
OpenPDK was an attempt to “standardize” PDKs and get them away from proprietary EDA vendor formats. So you could have one common DRC deck, one LVS deck, one primitive library definition that worked with all EDA tools. The primary beneficiary of this would have been the fabs themselves who could save development and validation costs developing multiple PDKs for each EDA vendor. This effort really didn’t go anywhere (that I know of).
This article is about an Open Source PDK, which is something different. It appears to be a PDK developed by volunteers and industry experts, not directly affiliated with the fab. To me, this seems more like a case of the fab (SkyWater) trying to save PDK development costs by outsourcing it to the Open Source community. An interesting concept, for sure, but probably not as revolutionary as the article makes it sound.
Fabs will not charge anyone for their PDKs. Yes, they will make you sign an NDA (a PDK does contain proprietary information related to their groundrules and device characteristics, which they are protective of). And you may run into resistance from the fab to provide you the PDK unless you can convince them that you are in fact planning on taping out a part with them. They have limited support teams and can’t afford to give everyone and their brother access to the PDK only to get bombarded with questions. But if you are going to be building a part with them, they will happily provide you with a PDK free of charge. So this development is not some kind of new opening of technology to the unwashed masses.
As for IP libraries such as standard cells and IOs, those too are usually available free of charge. The typical business arrangement is that the fab pays a royalty to the library provider that they get from your wafer costs. Again, you’ll need to sign an NDA and be “approved” after they are sure you’re really building something and aren’t just kicking tires and creating a support burden. There are truly open source IP libraries out there as well, but usually these would be higher level macros delivered as RTL.
Finally as to 130µm technology…yeah, it’s not leading edge lithography, but there is still plenty of development going on at that node (and higher). No one should make the assumption that this is not a very usable node, especially for smaller organizations with little ASIC design experience.
Reasonable explanation.
Nice, well put summary, but let’s not gloss over the BIG elephant in the room …
As you put it: “you may run into resistance from the fab to provide you the PDK unless you can convince them that you are in fact planning on taping out a part with them” … Well, truer words could hardly have been spoken.
For those of us interested in doing something in this field, be it a SW tool or a chip of some kind, who unfortunately do not have a large trust fund to their names and can show some juicy financial statements to the fab to convince them to share their proprietary PDK, the chances of actually getting anything from them are pretty much nilch.
An actual open source PDK with concrete numbers in it relating to the fabrication process, rules, and what not, is therefore a significant step and an unprecendented one at that. And let’s be honest, it’s only possible because a large company like Google is behind it, and it’s their clout that convinced Skywater to release its geometries.
I don’t know what will become of this project, but I’ll keep my fingers crossed that it will stay alive long enough to see some actual development from the community.
Well sure, it’s a big elephant in the room, but if you’re not able to actually build something with the fab, what’s the point in using an actual fab’s PDK to just play around with?
If you’re a digital designer looking to play around with Verilog, you can go pretty far without even needing to synthesize to a standard cell library. You can just stick with RTL and maybe even target an FPGA to try out your design concept. If you get to the point where you actually need to target a specific process for some reason, it seems like it’s probably time to start fundraising or partnering up with a shop that can foot the bill to actually implement your design in hardware.
If you’re an analog designer, maybe you want some realistic device models to try out your latest circuit, but again, once you get to the point of needing specific process models, aren’t you getting to the point of committing to building something?
Maybe you can help me understand the use case here. Are we talking about a hobbyist playing around a bit, maybe developing skills, or are we talking about a brand new startup that is looking to do a proof of concept in the hopes of eventually fabricating something?
If the former, you can probably get by with generic models, while if the latter, I would think that a MOSIS registration would be within reach, giving access to a wide variety of PDKs.
My first ASIC from this program just arrived!
https://www.youtube.com/watch?v=XEjc5ppRJuw