With VHDL being arguably more deterministic and bullet-proof than Verilog, it’s good to see another open source VHDL simulator joining the fray that is not a variation of ghdl. Written by [Óscar Grimal] in C++ with an MIT license, the Pulse project is a still in progress package that provides the entire toolchain, from the compiler to the requisite waveform output.
This waveform output is provided in the form of a text-based user interface (TUI), which at the very least helps a lot with making it cross-platform compatible. As dependencies only a C++20 capable compiler and CMake are indicated.
Of course, with VHDL being a rather hefty language especially once you start piling up the associated standard library, the currently supported language and library features are somewhat limited still so that you’re limited to basic IEEE packages and types, with default values are not supported yet.
Per the roadmap on the GitHub project’s Readme more VHDL language features including generics and additional types will be added, along with an enhanced simulation engine. It’s also said that mixed-language support with Verilog will be added, though SystemVerilog looks to be getting the short end of the stick as usual.
It will definitely be interesting to compare this package to ghdl.
It looks weird how the example project does not appear to be valid VHDL at all:
https://github.com/oscar30gt/pulse/blob/main/test-project/counter.vhd
(needed libs are not even imported, the clocked process with ‘clk = “1”‘ seems rather weird, and std_logic_vector being incremented seems like it doesn’t do type safety)
The main feature I love about GHDL is that what compiles with it is usually valid and portable VHDL. Many vendor toolchains accept a lot of weird non-standard stuff and then you hit problems if you try to switch to another vendor.
But maybe this is geared more towards learning & educational projects for now, where you don’t need the code to actually pass any synthesis tool and are just practicing basic VHDL syntax.
I would hope these are just temporary hacks to get the software boot strapped. It’s hard to implement anything thing in the compiler without a working simulator, and vice verse.
In fact, I don’t see anything too wrong with the example. The clk = 1 statement is a comparison, so is fine right?
Not certain on the addition operation – I’m rusty on what you can and can’t do with std_logic_vector with recent vhdl standards.
Either way, it seems it’s in early development still, so we shouldn’t be too surprised to see gribblies.
That said, I wonder why anyone needs this. If it’s simply that the author wanted to do it, then that makes perfect sense, but I wouldn’t bother switching even if it did everything it says it will do in the roadmap. If it aint broke…
It is long time since i used VHDL so neede to check some of my old stuff and yes, there is some weirdness.
Missing imports is one.
And the the sequential process is also strange as the idiom for clocked register is:
if rst = ‘1’ then
elsif clk’event and clk = ‘1’ then
end if;
at least when you want the designe to be synthetized into FPGA
and x”00000000″; can be written as simply 1 but both should work
VHDL is very idiomatic when it comes to syntesis. Lot of syntactically correct ways to write something but only one correct way if you want to suntesize the design. The reigster proicess is one of them, another example would be 3 process FSMs and there are more (like inferred memory or hw multipliers for example).
The process has a sensitivity list, that includes clk. So that there has been an event on clk is implied. So it is correct to test only that clk=1
You can’t assign 1 to a vector of std_logic elements. You need unsigned or similar for that.
Actually, I take that back – rst is also on the list, so it isn’t certain that an event has occured on clk. It is still synthesisable though. But latches will be inferred.
That’s the deterministic and bullet-proof part of the HDL…
While it is good to see another simulator option coming up, itwill take a while until that tool will reach a usable level.
I wonder why they haven’t instrad contributed to the NVC VHDL simulator instead of building another one in C/C++?
The NVC guys are rather difficult to work with, I just took their repo and did my own thing with it –
https://github.com/kev-cam/sv2ghdl/blob/main/bfit/benchmarks/gpu_farm.md
https://github.com/kev-cam/nvc
that’s the fastest all-round simulator you can get, and the most capable.