With VHDL being arguably more deterministic and bullet-proof than Verilog, it’s good to see another open source VHDL simulator joining the fray that is not a variation of ghdl. Written by [Óscar Grimal] in C++ with an MIT license, the Pulse project is a still in progress package that provides the entire toolchain, from the compiler to the requisite waveform output.
This waveform output is provided in the form of a text-based user interface (TUI), which at the very least helps a lot with making it cross-platform compatible. As dependencies only a C++20 capable compiler and CMake are indicated.
Of course, with VHDL being a rather hefty language especially once you start piling up the associated standard library, the currently supported language and library features are somewhat limited still so that you’re limited to basic IEEE packages and types, with default values are not supported yet.
Per the roadmap on the GitHub project’s Readme more VHDL language features including generics and additional types will be added, along with an enhanced simulation engine. It’s also said that mixed-language support with Verilog will be added, though SystemVerilog looks to be getting the short end of the stick as usual.
It will definitely be interesting to compare this package to ghdl.
It looks weird how the example project does not appear to be valid VHDL at all:
https://github.com/oscar30gt/pulse/blob/main/test-project/counter.vhd
(needed libs are not even imported, the clocked process with ‘clk = “1”‘ seems rather weird, and std_logic_vector being incremented seems like it doesn’t do type safety)
The main feature I love about GHDL is that what compiles with it is usually valid and portable VHDL. Many vendor toolchains accept a lot of weird non-standard stuff and then you hit problems if you try to switch to another vendor.
But maybe this is geared more towards learning & educational projects for now, where you don’t need the code to actually pass any synthesis tool and are just practicing basic VHDL syntax.