Add A Bit Of Soviet-Era Super-Computing To Your FPGA

The MESM-6 project is focused on bringing the 1960s Soviet BESM-6 computer to the modern age of FPGAs and HDLs. At the moment the team behind this preservation effort consists out of [Evgeniy Khaluev], [Serge Vakulenko] and [Leo Broukhis], who are covering the efforts on the Russian-language project page.

The BESM-6 (in Russian: БЭСМ-6, ‘Bolshaya Elektronno-Schetnaya Mashina’ or ‘large electronic computing machine’) was a highly performing Soviet super computer that was first launched in 1968 and in production for the next 19 years. Its system clock ran at 9 MHz using an astounding number of discrete components, like 60,000 transistors and 170,000 diodes, capable of addressing 192 kB of memory in total. Of the 355 built, a few survive to this day, with one on display at the London Science Museum (pictured above). Many more images and information can be found on its Russian Wikipedia page.

For those not gifted with knowledge of the Russian language, the machine-translated summary reveals that the project goal is to make a softcore in SystemVerilog that is compatible with user mode BESM-6, using the same Pascal compiler as originally used with that system. Further goals include at least 24 kB of data memory, 96 kB of command memory and the addition of modern peripherals such as SPI and I2C.

The system is meant to be integrated with the Arduino IDE, using the Pascal compiler to make it highly accessible to anyone with an interest in programming a system like this. Considering the MIT license for the project, one could conceivably use a bit of Soviet-era computing might in one’s future FPGA efforts.

If after watching the BESM-6 video — included below — you feel inspired to start your own Soviet-computing project, we’d like to wish you luck the Russian way: Ни пуха ни пера!

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Sort Faster With FPGAs

Sorting. It’s a classic problem that’s been studied for decades, and it’s a great first step towards “thinking algorithmically.” Over the years, a handful of sorting algorithms have emerged, each characterizable by it’s asymptotic order, a measure of how much longer an algorithm takes as the problem size gets bigger. While all sorting algorithms take longer to complete the more elements that must be sorted, some are slower than others.

For a sorter like bubble sort, the time grows quadradically longer for a linear increase in the number of inputs; it’s of order O(N²).With a faster sorter like merge-sort, which is O(N*log(N)), the time required grows far less quickly as the problem size gets bigger. Since sorting is a bit old-hat among many folks here, and since O(N*log(N)) seems to be the generally-accepted baseline for top speed with a single core, I thought I’d pop the question: can we go faster?

In short — yes, we can! In fact, I’ll claim that we can sort in linear time, i.e a running time of O(N). There’s a catch, though: to achieve linear time, we’ll need to build some custom hardware to help us out. In this post, I’ll unfold the problem of sorting in parallel, and then I”ll take us through a linear-time solution that we can synthesize at home on an FPGA.

Need to cut to the chase? Check out the full solution implemented in SystemVerilog on GitHub. I’ve wrapped it inside an SPI communication layer so that we can play with it using an everyday microcontroller.

To understand how it works, join us as we embark on an adventure in designing algorithms for hardware. If you’re used to thinking of programming in a stepwise fashion for a CPU, it’s time to get out your thinking cap!

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