[James Bowman] of the Willow Garage published a paper on his J1 CPU core for field-programmable gate arrays. This was originally developed and used for the Ethernet cameras on the PR2 (you know, that incredibly expensive beer delivery system?) robot. It uses a 16-bit von Neumann architecture and lacks several processor features you’d expect a CPU to have such as interrupts, multiply and divide, a condition register, and a carry flag. None-the-less, its compact at just 200 lines of Verilog and it can run at 80 MHz. [James] compares the J1 to three different FPGA CPU Cores commonly used and discusses how the system is built in his 4-page paper that has the details you’re interested in but won’t take all day to dig through.
[Chris] sent us this project, where he built a tiny supercomputer called the Non-von1. Wanting a supercomputer, but lacking space and funds, he opted to go after the supercomputers of the 80s. His system was patterned after the “Von Neumann” systems developed at Columbia university. His system has 31 8 bit processors to crunch numbers for him. The whole unit communicates with the computer using a19.2 kbps serial link. He does talk about its limited capabilities, stating that he could use it as a way to store roughly half of his cell phone’s phonebook. This reminds us of the Basic stamp supercomputer we covered back in November.