In part one, I compared the different Analog to Digital Converters (ADC) and the roles and properties of Delta Sigma ADC’s. I covered a lot of the theory behind these devices, so in this installment, I set out to find a design or two that would help me demonstrate the important points like oversampling, noise shaping and the relationship between the signal-to-noise ratio and resolution.
Check out part one to see the block diagrams of what what got us to here. The schematics shown below are of a couple of implementations that I played with depicting a single-order and a dual-order Delta Sigma modulators.
Basically I used a clock enabled, high speed comparator, with two polarities in case I got it the logic backwards in my current state of burn out to grey matter ratio. The video includes the actual schematic used.
Since I wasn’t designing for production I accepted the need for three voltages since my bench supply was capable of providing them and this widget is destined for the drawer with the other widgets made for just a few minutes of video time anyway.
In Search of Digital Filters
I also was attracted to the Cypress PSOC-5 as it had all of the components that make up the modulator plus they have a digital filter component that can be instantiated and programmed. Alas, it was a Finite Impulse Response (FIR) type which, although more common, isn’t a Cascade Integrator Comb (CIC) filter which we need.
This looks to be a cheap and powerful way to get exposed to digital filters and includes a workbench for generating the mathematical coefficients that drive a filter. I also wanted to show different ways to generate the coefficients, but simply ran out of time and space. I see a Hackaday post about FIR and other digital filters in the future.
Ultimately I chose to use a standalone Delta Sigma Modulator IC AD7403 made by Analog Devices as a clean example of what I am trying to demonstrate. (While writing this post I learned that Analog Devices just acquired Linear Tech which scares me. I like the diversity of competition and still pine for the days when I would pull down a databook for Precision Monolithics, Elentac, or Intersil depending on what I was up to. I also miss National … a lot.) But back to our modulator…
This particular module also has a cool feature in in that the ADC portion of the chip is isolated from the digital output portion, so much so that there are two sets of power pins including two grounds with no connectivity between them. This is useful in instrumentation or automation where the isolation is used to protect the digital back end equipment from the hostile environment the sensors are exposed to. As an example, picture shorting 480 Volts to an analog signal and NOT blowing out the computer that processed the signal from the ADC. Someone had previously asked about the isolation implied by the 4-20ma current loop standard, this is an example of a part you might use to achieve that isolation.
Once again looking at the modulator output we see the single bit representation of the original signal, and then the oscilloscope reconstructing the signal by averaging.
Averaging actually performs a similar function to the first step of the digital processing we need to do. Looking at the block diagram just below in the DSP section, what we need to do is accumulate a bunch of samples, and then thin them back down, or decimate them, to just what we need. The act of integrating allows us to accumulate the positive effects of oversampling and also provides the noise shaping, resulting in two noise reduction techniques right off the bat.
Sample Rate Conversion
As an aside, having an averaging/integrating function followed by a decimating function is basically how sample rate conversion works. For example converting from the audio CD standard of 44.1K samples per second to the DAT/DVD 48k rate, the 44.1ksps is first accumulated (multiplied) by a value of 160 and then decimated (divided) by 147 to get the end result of 48k.
Digital Signal Processing (DSP)
Here is a block diagram depicting the stages of the CIC filter. This is fairly standard way of depicting the operations in DSP-speak, the summation blocks show simple adding and subtracting and the blocks marked Z are basically clocked register storage. You can see that a series of these registers is a pipeline of intermediate results with operations between them.
A lot of DSP implementations work this way, there is an inherent delay in getting the first result as it has to clock its way through all of the stages but then an answer is available on each subsequent clock. That is, there is usually some latency but also high throughput when using pipelined architectures.
Looking at the block diagram, one of the advantages to using a CIC filter over slightly more complicated filter topologies is that there is no multiplication or division needed, just addition and subtraction. Multipliers and dividers require more hardware to implement in hardware, just as there would be more instructions needed for multiplication if implementing in software.
It should be noted that the CIC function here can be implemented in software, with the difference being that it takes many processor clock cycles to yield a result. The hardware DSP provides a value every clock cycle. There are other inherent differences between hardware and software implementations of filters in general, and arguing about them has passed many an hour at the local bistro.
DSP in FPGA
One of the topics here at Hackaday is asking what FPGA’s are good for given the versatility, performance, availability and price of microprocessor or microcontroller based hardware. Digital Signal Processing is one area were once you step up to an FPGA implementation you may have lots of options such as multiple conversions in parallel or complex functions that still provide an answer every clock cycle.
I found many examples of CIC filters written in Verilog and VHDL on the net but a straightforward example was included right in the datasheet for the AD7403. They even include the block diagram which matches ours. I cleaned up some of the typos in the Verilog as there was probably an OCR step somewhere along the way in the creation of the datasheet for AD7403: CIC Filter in Verilog.
This file is now the basic building block of our CIC filter and can be used in any of the available FPGA design suites. As I have my Altera Quartus already loaded and a target board with a Cyclone IV handy so I will be using Quartus. Quartus has a free to use version which is close enough to open source for me and it includes the powerful ModelSim simulator . I swear I will try and get to a Lattice version some time when I am not already behind schedule.
Create the FPGA Project
Step one was to create a project directory and save a copy of the CIC filter text file written in Verilog there. The next step was to run the New Project Wizard and select the EP4CE6E22C8 which is a 144 Pin version of a Cyclone IV on my target board.
Next I imported the pin assignments I have made for this particular FPGA development board, though I didn’t really use of the static pin assignments in this exercise other than the global clock. <Assignments, Import, Select file>
Next is to add the Verilog file to the project. <Files, Add File to Project, select file>
A personal preference of mine is to work with a graphical top sheet for a design and show the pins and files as interconnected blocks. This allows me to easily visual pin assignments, add simple inversions or other intuitive logic, and also add test points or other temporary functions that I can then remove later.
To do this with a Verilog file I create a symbol file for it for use in the top level graphical sheet.which compiles the Verilog file and if successful, creates the symbol.
Insert the Block
The final steps consists of inserting the block <Insert, Symbol, select file>, and placing it on the sheet. A quick shortcut provided by using this method is that I can auto-generate the pins by selecting the symbol and then <Generate Pins for Symbol Ports>.
I can then optionally assign pin numbers if I want or I can let the compiler create pin assignments. Letting the compiler decide on pins is often not possible late in the design cycle when consistency is needed, however allowing the compiler to select assignments and other resources during an initial pass often can yield a more optimized use of FPGA resources.
Connect, Compile and Program
That’s it for creating an FPGA design from a HDL file assuming that there is no optimization or debugging needed. The next steps are to do the final compilation and program the part. <Processing, Start Compilation> <Programmer, select file, Start>
Using a Wizard to Make a Filter
Quartus includes a library of high-level components such as DSP filters that you can use for free as long as the programmer is plugged in to the development board. I know that Xilinx includes similar features in their design suites but I haven’t used them recently enough to say more.
So in essence we can build a CIC DSP filter without writing a single line of code. Open the system builder Qsys <tools, qsys=””> . The CIC filter can be installed by opening the Library from the IP Catalog and under the DSP heading select CIC under Filters. On the right hand side the various parameters may be selected to create the variation of the filter we are interested in.
Finally we set up the interconnect and export the inputs and outputs as ports (best to watch the video for this part) and click <Generate HDL>, select <Verilog> and then click . As the box was checked we will get both the Verilog text file and a symbol as we did in the previous example.
From here it’s just like the previous example, you instantiate the symbol representing the Qsys design and hook it to pins, compile and program.
AD7760 Evaluation Board
And finally I wanted to show some interaction with some of the variables such as decimation rate and average size. Using a development board and a motherboard made to couple to it I am able to display the output of the AD7760 24-bit Delta Sigma ADC. The interface allows me to adjust the various parameters and observe them and then also display in real time things like the calculated Signal to Noise Rate (SNR) and the Total Harmonic Distortion (THD). Again I recommend checking out the video as this is somewhat interactive.
As a parting shot I select the modulator output in the frequency domain and there is our noise shaping that we know is built into the design of Delta Sigma converters.
Delta Sigma Omega
The Delta Sigma Analog to Digital Converter demonstrates a combination of technologies that works together to improve speed and resolution beyond what a single technique alone could achieve. It also benefits from both analog and digital noise reduction techniques in its role of bridging analog and digital domains.
- Analog Devices AD7403 Datasheet
- Principles of Sigma-Delta Modulation for Analog-to Digital Converters (Motorola)
- How delta-sigma ADCs work, Part 1 (TI)
- How delta-sigma ADCs work, Part 2 (TI)
- TSA002 – 16-bit Sigma Delta ADC Design
- FPGA based sigma –Delta analogue to digital converter design
- Exploring Decimation Filters
- Combining the ADS1202 with an FPGA Digital Filter for Current Measurement in Motor Control Applications
- Verilog Fundamentals
- CIC Filter Introduction
- Understanding CIC Compensation Filters (Altera)
- Demystifying Delta-Sigma ADCs
- TSP #32 – Tutorial on the Theory, Design and Measurement of Delta-Sigma Analog to Digital Converters – YouTube (Really good, includes the math)