What do you get if you cross graphene, hexagonal boron nitride, and tungsten diselenide? Well, according to researchers at Hunan University, you get a field effect transistor that can act as both a switching element or a memory cell. The partial floating-gate field-effect transistor or PFGFET uses 2D van der Waals heterostructures to deal with isolated atomic layers. The paper in Nature is unfortunately behind a pay wall, but you can read a summary over on [TechExplore].
The graphene acts as the gate, and the transistor can be switched between n-type behavior and p-type behavior. It can also be configured as a switching element or as a memory element similar to an EEPROM cell.
One advantage of having configurable transistor types is that a single transistor structure can produce CMOS or complementary circuits. Traditionally, a CMOS IC has two different transistor structures and often producing one of them requires extra effort.
The configuration takes place by applying a control voltage pulse. A negative control voltage produces a p-type FET and a positive voltage configures the same transistor as an n-type. If you don’t have access to the paper, the figures available online offer a good bit of insight into the device’s design.
If you want to learn more about ordinary MOSFETs, we talk about them often. You can also get the skinny on CMOS from [Bil Herd].
Typo, must be “Van der Waals” instead, not walls.
Van Darkholme’s Balls are the thing every man wants.
Love that Oasis song
Perfect to annoy Richard Hammon lol
Van-sama? uWu
It’s behind a pay waal :)
You are right. I suspect autocorrect bit me.
Nice new idea. Or I assume it’s new anyway.
I didn’t see anything about non-volatility across power cycles, or deterioration over time.
It also seems this thing is very slow in its programming behavior.
In the non-paywalled parts it doesn’t look like they include switching times, which might mean it’s “fast enough” or something that is better not disclosed for fear of not getting further funding.
maybe capable of making denser sram, which would be a boon to your cpu cache.
A CPU that reconfigures itself as bugs are found.
Seems well suited for FPGA fabric. I’m not sure if it’s superior to the current technology though. Maybe with a different architecture.
Cool…
Maybe a solution for compute-in-memory for use in AI hardware?
I dunno, I only learned about compute in memory concepts a week ago.
Maybe I’m crazy or just dumb ¯\_ (ツ)_/¯
Off we go to scihub….