Editing Your FPGA Source

July 22, 2012 by Brian Benchoff 18 Comments

[Dave] noted that in a recent poll of FPGA developers, emacs was far and away the most popular VHDL and Verilog editor. There are a few reasons for this – namely, emacs comes with packages for editing your HDL of choice. For those of us not wanting to install (and learn) the emacs operating system, [Dave] got Notepad++ to work with these packages.

Notepad++ already has VHDL and Verilog highlighting along with other advanced text editor features, but [Dave] wanted templates, automated declarations and beautification. To do this, he used the FingerText to store code as snippets and call them up at the wave of a finger.

As [Dave] writes his code, the component declarations constantly need to be updated, and with the help of a Perl script [Dave] can update them with the click of a hotkey. Beautification is a harder nut to crack, as Notepad++ doesn’t even have a VHDL or Verilog beautifier plugin. This was accomplished by installing emacs and running the beautification process as a batch script. Nobody can have it all, but we’re thinking [Dave]’s method of getting away from emacs is pretty neat.

Programming FPGAs With Python

June 11, 2012 by Brian Benchoff 22 Comments

If you’ve ever wanted to jump into the world of FPGAs but don’t want to learn yet another language, you can now program an FPGA with Python. PyCPU converts very, very simple Python code into either VHDL or Verilog. From this, a hardware description can be uploaded to an FPGA.

The portion of the Python language supported by PyCPU is extremely minimal, with only ints being the only built-in data type supported. Of course ifs and whiles are still included along with all the assignments and operators. A new addition is a way to get digital IO access with Python, and obvious requirement if you’re going to be programming Silicon.

PyCPU surely won’t replace VHDL or Verilog anytime soon, but if you’re looking to get into FPGAs and the ‘telling a chip what to be’ paradigm it offers, it’s certainly a tool worth looking into.

Hats off to [hardsoftlucid] for sending this in. Our wonderful (we mean that, really) noticed a few mistakes when this was first posted. Those mistakes have been corrected.

Building A One-instruction Computer

July 27, 2011 by Brian Benchoff 23 Comments

[Hasith] sent in this project where he goes through the process of designing a one instruction CPU in Verilog. It may not win a contest for the coolest build on Hack A Day, but we really do appreciate the “applied nerd” aspect of this build.

With only one instruction, an OISC is a lot simpler than the mess we have to deal with today. There are a few instructions that by themselves are Turing-complete (like Subtract and branch if negative, and Move). Designing an OISC with one of these instructions means it can also emulate a Turing machine.

Continue reading “Building A One-instruction Computer” →

J1: A Small, Fast, CPU Core For FPGA

December 1, 2010 by Mike Szczys 25 Comments

[James Bowman] of the Willow Garage published a paper on his J1 CPU core for field-programmable gate arrays. This was originally developed and used for the Ethernet cameras on the PR2 (you know, that incredibly expensive beer delivery system?) robot. It uses a 16-bit von Neumann architecture and lacks several processor features you’d expect a CPU to have such as interrupts, multiply and divide, a condition register, and a carry flag. None-the-less, its compact at just 200 lines of Verilog and it can run at 80 MHz. [James] compares the J1 to three different FPGA CPU Cores commonly used and discusses how the system is built in his 4-page paper that has the details you’re interested in but won’t take all day to dig through.