This frequency counter is [Miguel Pedroso's] entry in the 7400 Logic contest. After looking at the design we think this is a perfect project for those who have not worked with logic ICs before. The concept is simple and [Miguel] does a great job of explaining his implementation.
At its heart the device simply counts the oscillations of an input signal for one second, then latches the total to the 7-segment displays before zeroing the counter block and starting over. Six 4029 decade counters give the device a range of 1MHz. A set of 4511 BCD to 7-segment decoders translate the count to the display. A 4521 frequency divider chip uses an on-board 4.194304 MHz crystal oscillator to time both the display latching and the counter clearing. [Miguel] mentions that tuning the load capacitors is a bit tricky. Since breadboards have their own capacitance issues it may be necessary to change the load capacitor values when moved to protoboard or the crystal won’t start oscillating. You can see those caps are not the same value, but the tests in the video after the break show that this is pretty much spot-on.
If you’d rather give this a try in HDL here’s an FPGA-based frequency counter from which you can draw some inspiration.