Building a software defined radio (SDR) involves many trades offs. But one of the most fundamental is should you use an FPGA or a CPU to do the processing. Of course, if you are piping data to a PC, the answer is probably a CPU. But if you are doing the whole system, it is a vexing choice. The FPGA can handle lots of data all at one time but is somewhat more difficult to develop and modify. CPUs using software are flexible–especially for coding user interfaces, networking connections, and the like) but don’t always have enough horsepower to cope with signal processing tasks (and, yes, it depends on the CPU).
[Eric Brombaugh] sidestepped that trade off. He used a board with both an ARM processor and an ICE FPGA at the heart of his SDR design. He uses three custom boards: one is the CPU/FPGA board, another is a 10-bit converter that can sample at 40 MSPS (sufficient to decode to 20 MHz), and an I2S DAC to produce audio. Each board has its own page linked from the main project.
You can find the C and Verilog sources for the device on GitHub. [Eric] also has a great block diagram and description of how everything works available. So far, the device can handle AM, synchronous AM, narrow-band FM, as well as upper and lower sideband (or both at once). It can also send raw IQ signals directly out for further processing.
Oddly enough, we haven’t talked about [Eric’s] design before, but a picture of it appeared in a past post about (among other things) the PMOD connector system (since the DAC uses PMOD as its interface). [Eric’s] device handles about 20 kHz of bandwidth at a time. If you want something more (also with an FPGA), check out FreeSRP.