Some of us have felt somewhat nervous about the collapse of DRAM and NAND Flash memory supply in the consumer market, while others seem to have fully embraced it. Someone like [polymatt] for example, whose recent project entails a USB drive that skips back quite a few decades and opts to use a glorious 64-bit core memory device for storage.
To really embrace the DIY spirit here, the PCBs were milled using a small CNC router before the core memory was assembled alongside the other components, including apparently L293 H-bridge ICs as the drivers, along with an ESP32 module for the brains and USB interface.
Much like NAND Flash, core memory relies on sensing the state of a cell through a destructive read action, which thus requires a fair bit of surrounding logic to set up read and writes, parse sense line values and restore any read value after said destructive read. Determining the right voltage to use during read and write actions is essential, and here determined experimentally.
The final build contains two PCBs inside an enclosure that’s filled with silicone oil. Other than looking cool through the acrylic window, it also helps to keep the individual cores at a fairly consistent temperature, which is helpful with reliable bit flipping, even if it’s probably overkill here.
Ignoring for a moment that just the memory required for the USB stack in the ESP32 module is many times the size of this core memory device, it’s still a very cool project whose appeal goes far beyond mere practicality.
TSMC and Winbond are collaborating on a localized DRAM supply chain using 3D wafer-on-wafer (WoW) stacking technology, where Winbond would supply DRAM memory wafers to be stacked with TSMC’s logic wafers. The move is designed to keep critical memory production close to home while feeding the demand of AI hardware.
Key details:
The tech: WoW uses hybrid bonding to directly stack logic chips and memory wafers vertically, creating tens of thousands to millions of micro copper interconnects — shortening data transmission distance versus traditional packaging, with higher bandwidth, lower latency, and better power efficiency. It's positioned as critical for AI servers, HPC, and edge AI devices.
Why Winbond: TSMC's WoW memory wafers have historically relied on Samsung, SK Hynix, and Micron. With global memory supply extremely tight and those three running near full capacity, TSMC is diversifying. Winbond's long track record in niche/specialty DRAM and NOR Flash, plus its mature 12-inch wafer production, high yield, and quality control, made it a fit.
Strategic angle: This is framed as TSMC cultivating a domestic supply chain to strengthen Taiwan's self-sufficiency in AI chip components — elevating Winbond from a peripheral player to a core part of the global AI supply chain, and reinforcing Taiwan's overall position in AI semiconductor manufacturing.
Caveat: Winbond declined to comment on specific clients/deals, and TSMC had not responded by press time — this is sourced to unnamed industry insiders, not confirmed by either company.
Some more technical color on what Winbond actually brings:
Several outlets cite Winbond's proprietary architecture called CUBE (Customized Ultra-Bandwidth Elements), described as purpose-built for WoW integration, with scalable memory density from 256Mb to 8Gb per die. Crypto Briefing
Why now? Well, as everyone knows by now, the memory pricing backdrop is extreme, if not outright absurd, with all demand crushed except for (off-balance sheet_ debt-funded data centers .One analysis flagged that DRAM prices rising nearly 75% in early 2026, and with the memory crunch expected to persist until at least 2027, that's the real catalyst pushing TSMC to diversify away from Samsung/SK Hynix/Micron.
This is not Winbond's first rodeo on this front. Separately, Winbond has also been building a DRAM foundry partnership with Elpida targeting graphics DRAM, not cutting-edge HBM — framed by one analyst as a resilience/diversification move for Taiwan's supply chain rather than a direct challenge to Korean HBM dominance.
Now, After reading that…. What if the folks started doing WHOLE DIE VLSI… Top surface, Bottom surface and all four edges…. Then the WoW idea can really scale up a bit and still allow thermals to be dealt with in normal way.
If a Die has 4GB area at a process, than by simple math you can see by doing both sides of the die in NAND you get to use the area to the fullest.
It’s what 63.2% of the wafer is wasted… and those edges can offer power and buss work for WoW.
And after thinking that…. Think, Wafer Edge connect and structures like Regular dodecahedron construction and liquid cooling….
If i was going to get freaky with the WoW concept.
Sort of other end of the memory spectrum…. But a cool idea none the less with this Wafer on Wafer process.