CPU ISA

3 Articles

Checking In On The ISA Wars And Its Impact On CPU Architectures

March 18, 2025 by 33 Comments

An Instruction Set Architecture (ISA) defines the software interface through which for example a central processor unit (CPU) is controlled. Unlike early computer systems which didn’t define a standard ISA as such, over time the compatibility and portability benefits of having a standard ISA became obvious. But of course the best part about standards is that there are so many of them, and thus every CPU manufacturer came up with their own.

Throughout the 1980s and 1990s, the number of mainstream ISAs dropped sharply as the computer industry coalesced around a few major ones in each type of application. Intel’s x86 won out on desktop and smaller servers while ARM proclaimed victory in low-power and portable devices, and for Big Iron you always had IBM’s Power ISA. Since we last covered the ISA Wars in 2019, quite a lot of things have changed, including Apple shifting its desktop systems to ARM from x86 with Apple Silicon and finally MIPS experiencing an afterlife in  the form of LoongArch.

Meanwhile, six years after the aforementioned ISA Wars article in which newcomer RISC-V was covered, this ISA seems to have not made the splash some had expected. This raises questions about what we can expect from RISC-V and other ISAs in the future, as well as how relevant having different ISAs is when it comes to aspects like CPU performance and their microarchitecture.

Continue reading “Checking In On The ISA Wars And Its Impact On CPU Architectures” →

Tesla’s Dojo Is An Interesting CPU Design

September 6, 2022 by 29 Comments

What do you get when you cross a modern super-scalar out-of-order CPU core with more traditional microcontroller aspects such as no virtual memory, no memory cache, and no DDR or PCIe controllers? You get the Tesla Dojo, which Chips and Cheese recently did a deep dive on.

It starts with a comparison to the IBM Cell processors. The Cell of the mid-2000s featured something called the SPE (Synergistic Processing Elements). They were smaller cores focused on vector processing or other specialized types of workloads. They didn’t access the main memory and had to be given tasks by the fully featured CPU. Dojo has 1.25MB of SRAM that it can use as working memory with five ports, but it has no cache or virtual memory. It uses DMA to get the information it needs via a mesh system. The front end pulls RISC-V-like (heavily MIPS-inspired) instructions into a small instruction cache and decodes eight instructions per cycle. Continue reading “Tesla’s Dojo Is An Interesting CPU Design” →

ORNL's Summit supercomputer, fastest until 2020 (Credit: ORNL)

Joining The RISC-V Ranks: IBM’s Power ISA To Become Free

August 23, 2019 by 38 Comments

IBM’s Power processor architecture is probably best known today as those humongous chips that power everything from massive mainframes and supercomputers to slightly less massive mainframes and servers. Originally developed in the 1980s, Power CPUs have been a reliable presence in the market for decades, forming the backbone of systems like IBM’s RS/6000 and AS/400 and later line of Power series.

Now IBM is making the Power ISA free to use after first opening up access to the ISA with the OpenPower Foundation. Amidst the fully free and open RISC-V ISA making headway into the computing market, and ARM feeling pressured to loosen up its licensing, it seems they figured that it’s best to join the party early. Without much of a threat to its existing business customers who are unlikely to whip up their own Power CPUs in a back office and not get IBM’s support that’s part of the business deal, it seems mostly aimed at increasing Power’s and with it IBM’s foothold in the overall market.

The Power ISA started out as the POWER ISA, before it evolved into the PowerPC ISA, co-developed with Motorola  and Apple and made famous by Apple’s use of the G3 through G5 series of PowerPC CPUs. The PowerPC ISA eventually got turned into today’s Power ISA. As a result it shares many commonalities with both POWER and PowerPC, being its de facto successor.

In addition, IBM is also opening its OpenCAPI accelerator and OpenCAPI Memory Interface variant that will be part of the upcoming Power9′ CPU. These technologies are aimed at reducing the number of interconnections required to link CPUs together, ranging from NVLink, to Infinity Fabric and countless more, not to mention memory, where OMI memory could offer interesting possibilities.

Would you use Power in your projects? Let us know in the comments.