How To Build Your Own 16-Bit System-on-Spreadsheet

Back in the hazy days of theĀ  early home computers, many of us would rejoice at running our first BASIC applications, some of us even built our own 8-bit system from a handful of ICs and felt elated the moment the connected LEDs, screen or other output device would show signs of life. It is this kind of excitement that [Inkbox] has managed to bring to the bane of every office worker: spreadsheet programs like Excel. How, you may ask? Why, by implementing a completely functional 16-bit system with 16 general purpose registers, 128 kB of RAM and a 128×128 pixel color display, all inside an Excel spreadsheet, making it conceivably the world’s first System-on-Spreadsheet (SoS).

Perhaps the most tantalizing aspect of this approach is that it provides a very good visual way to indicate what is happening inside the system using color codes and clearly segregated and marked functional elements. Not only can it be programmed manually, but [Inkbox] also created an assembler for the CPU’s ISA – called Excel-ASM16 – all of which is available from the ExcelCPU GitHub project page. The ASM is assembled into a ROM.xlsx file that can then be run by the CPU.xlsx file by triggering the Read ROM button. After this you are confronted with the realization that although it all works, it’s also incredibly slow, at about 2-3 Hz.

Still, with all the elegance of an IMSAI 8080 front panel, we cannot help but give full points for this achievement. Plus it gives many of us something to do during those exceedingly dull meetings where only serious applications like office suites are allowed.

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NEO430 Puts A Custom MSP430 Core In Your FPGA

We are certainly spoiled by all the microcontroller options nowadays — which is a great problem to have. But between the good old 8-bit controllers and an increasing number of 32-bit varieties, it almost seems as if the 16-bit ones are slowly falling into oblivion. [stnolting] particularly saw an issue with the lack of 16-bit open source soft cores, and as a result created the NEO430, an MSP430 compatible soft processor written in VHDL that adds a custom microcontroller to your next FPGA project.

With high customization as main principle in mind, [stnolting] included a wide selection of peripherals and system features that can be synthesized as needed. Not limiting himself to the ones you would find in an off-the-shelf MSP430 controller, he demonstrates the true strength of open source soft cores. Do you need a random number generator, CRC calculation, and an SPI master with six dedicated chip select lines? No problem! He even includes a Custom Functions Unit that lets you add your own peripheral feature or processor extension.

However, what impresses most is all the work and care [stnolting] put into everything beyond the core implementation. From the C library and the collection of examples for each of the controller’s features, so you can get started out of the box with GCC’s MSP430 port, to writing a full-blown data sheet, and even setting up continuous integration for the entire repository. Each topic on its own is worth looking at, and the NEO430 offers a great introduction or reference for it.

Of course, there are some shortcomings as well, and the biggest downer is probably the lack of analog components, but that’s understandable considering your average FPGA’s building blocks. And well, it’s hard to compete with the MSP430’s ultra low-power design using an FPGA, so if you’re thinking of replicating this watch, you might be better off with a regular MSP430 from a battery lifetime point of view.

FPGA Soft CPU Is Superscalar

We will admit it: mostly when we see a homebrew CPU design on an FPGA, it is a simple design that wouldn’t raise any eyebrows in the 1970s or 1980s. Not so with [Henry Wong’s] design, though. His x86-like design does superscalar out-of-order execution, just like big commercial modern CPUs. Of course [Henry] designs CPU architectures for Intel, so that’s not surprising. You can see a very detailed talk on the design in the video, below. You can also read the entire thesis project.

[Henry] starts out with a description of FPGAs and soft processors. He also covers the use of multiple instruction issue to increase the virtual clock rate of a CPU. In other words, if a 100 MHz CPU can do one instruction at a time, it won’t be any faster — in theory — than a 50 MHz CPU that can do two instructions at once. Of course, trying to do two at once has some overhead, so that won’t be completely true.

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