RISC-V: Why The ISA Battles Aren’t Over Yet

A computer processor uses a so-called Instruction Set Architecture to talk with the world outside of its own circuitry. This ISA consists of a number of instructions, which essentially define the functionality of that processor, which explains why so many ISAs still exist today. It’s hard to find that one ISA that works for as many distinct use cases as possible, after all.

A fairly new ISA is RISC-V, the first version of which was created back in 2010 at the University of California, Berkeley. Intended to be a fully open ISA, targeting both students (as a learning tool) and industrial users, it is claimed to incorporate a number of design choices that should make it more attractive for a number of applications.

In this article I’ll take a look behind the marketing to take stock of how exactly RISC-V differs from other open ISAs, including Power, SPARC and MIPS.

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A FPGA Based Bus Pirate Clone

XC6BP

A necessary tool for embedded development is a device that can talk common protocols such as UART, SPI, and I2C. The XC6BP is an open source device that can work with a variety of protocols.

As the name suggests, the XC6BP is a clone of the Bus Pirate, but based on a Xilinx Spartan-6 FPGA. The AltOR32 soft CPU is loaded on the FPGA. This is a fully functional processor based on the OpenRISC architecture. While the FPGA is more expensive than a microcontroller, it can be fully reprogrammed. It’s also possible to build hardware on the FPGA to perform a variety of tasks.

A simple USB stack runs on the soft CPU, creating a virtual COM port. Combined with the USB transceiver, this provides communication with a host PC. The device is even compatible with the Bus Pirate case and probe connector. While it won’t replace the Bus Pirate as a low-cost tool, it is neat to see someone using an open source core to build a useful, open hardware device.