There is a phenomenon where as you get older, your sense of scale becomes somewhat fixed in the earlier era that shaped you– things like expecting the Dollar Store to carry items for 1$, or to get a burger and fries for less than twenty bucks– or, in this case, thinking of supercomputers as being petaflop-scale machines. That’s not wrong, per se– most of the world’s fastest machines benchmarks are best measured in petaflops– but when you’re clocking at 2198 of the things, it becomes easier just to say that the LineShine computer can do 2.188 exaflops. At double precision. With CPUs only. Yes, we are impressed.
Even more impressive is that this machine just debuted in China, which means it was built without the benefit of the latest-and-greatest Western chips, thanks to US sanctions. It’s using a made-in-China LX2 CPU with 304 ARMv9 cores onboard. Well, it’s actually using around 46 thousand of them, but who’s counting?
Each CPU actually consists of two separate compute dies and onboard high bandwith memory (HBM) and DRAM– 4GB of HBM and 32GB of DDR5. The 152 ARMv9 CPU cores on each chip are all built with Scalable Vector Extensions (SVE) and Scalable Matrix Extensions (SME), so despite the lack of GPUs LineShine will have no problem doing the sorts of vector processing that is traditional for high-performance computing, given the 13.79 million cores.
On the other hand, the lack of GPUs shows when you change benchmarks– LineShine is number one in the rankings for High Performance Linpack (HPL), but getting outside the 64-bit box, the supercomputer only hits number four on the HPL-MxP mixed-precision benchmark, behind machines that pair their CPUs with accelerators like GPUs or NPUs. That may mollify the American ego, as while their El Capitain was bumped to second place on the HPL list, they can still claim the pole position on HPL-MxP. Which computer is actually more capable depends entirely on what you want to do with it, and neither Lawrence Livermore National Laboratory nor China’s National Supercomputing Centre in Shenzhen advertise their compute queues, though this paper suggests at least one job will be crunching earth observation data.
The definition of a supercomputer has shifted over time, and it’s only a matter of time before LineShine and El Capitain end up on the auction block, like other supercomputers before them. We might question it when it comes to desktops, but for institutional HPC, no amount of computing ever seems to be enough.
My reference for a supercomputer is still the Cray-1. 80MHz 8Mb of RAM, costing USD 9M in 1977 and needing 115kW of electricity.
https://en.wikipedia.org/wiki/Cray-1
And then, a few decades later, some hobbyist re-created a working version in the size of a (beefy) keychain holder, rnning on a wallwart power supply. (Although it runs at a reduced 33MHz.)
https://hackaday.com/2012/01/10/help-chris-boot-his-cray-1-supercomputer/
I hear you! If I had a nickle for everytime I compared a microcontroller or piece of consumer electronics to a supercomputer, well… I’d be able to buy at least a few meals at McD’s, which isn’t chump change these days.
Also for comparison: The ESP32 (original version) is somewhat comparable in performance to an 80486. https://en.wikipedia.org/wiki/I486 That processor was released in 1989 and discontinued in 2007. The early ’80-ies were pretty crazy, from going from the Commodore 64 (1982) and MSX (1983) to the 80486 in the same decade.
And now we’re stuck with 3 to 5 GHz machines for already more then 20 years. In the early days I bought a new PC as soon as I could afford it. My last PC lasted 13 years, I expect my current PC to last more then that. PC’s are getting more processing cores, and that does help, but many programs still can not make good use of that.
Parallelism is a tough nut to crack.
…where do you think the “western chips” are made?
Intel fabs are in Arizona, Oregon, California, Ireland, Israel…
Where do you think they are made?
Taiwan, for most of the really good stuff.
Depending where on the globe you stand, you might consider them very far to the west indeed.
True. But some out there still think Taiwan is part of China.
Some? Most of the world to be precise.
Taiwan IS China and people there are Chinese. The only difference is they use their own government instead of merging with CCP.
Some of the natives might disagree.
Son of a gun. Looking a bit deeper, TSMC does make ITAR-controlled chips.
Amazing.
Since El Capitain is at the Lawrence Livermore National Laboratory (LLNL) in California. And it is funded by the U.S. Department of Energy, my guess would be that both supercomputers would be primarily dedicated to simulations of energy (Mostly Nuclear at a guess, for all applications including military).
A prepublication mentions Lineshine being use to create foundation models in hours rather than weeks or months. The times are a changing…
https://arxiv.org/html/2604.15821v1
Lineshine: 13.8 million cores, 42.2 megawatts, 2.2 exaflops
Per core: 3 watts, 159 gigaflops.
The CPU in the machine from 2015 that I’m writing this on:
i7-6700K: 8 cores, 45 watts, 17 gigaflops
Per core: 5.5 watts, 2.1 gigaflops.
So, 75 times the efficiency. Impressive.
But wait: Lineshine has a clock rate of 1.55 GHz, but can do 159 gigaflops per core. How on earth can one core do more than 100 floating point operations in a single clock cycle?
Probably predictionand paralism.
If it takes 8 cycles to make one operation, then maybe, if you start the second operation before the previous finished, you can eventually take the result of one operation (that started 8 cycles back) every cycle.
If you’re producing a sustained throughput of 100 floating point numbers per clock cycle, you need to move 6400 bits into, and 6400 bits out of the CPU on every clock cycle. Even with clocking on both edges this would take 6400 pins on each CPU.
I suppose that’s possible if the traffic is only to and from on-die memory, but even so, that’s pretty crazy interconnect.
Something isn’t quite as it appears here.
I found the answer in the definition: “A supercomputer is a computer that turns all compute-bound jobs into I/O-bound jobs. “
i don’t know any details about this architecture but in general, linear math (like linpack, or matrix multiply) performance in practice is dominated by cache use, for exactly this reason. no matter how much you optimize your memory pathway, the closer levels of cache are much faster than the further levels.
Matrix multiply doesn’t just stream the numbers through the multiply-add unit as fast as they can come from RAM (or disk or network), it actually re-uses each element several times in the computation. So there have been a variety of approaches over the years to split the computation up into blocks, with the blocks visited in such an order that you reuse the elements several times before it gets flushed from cache. I’m not sure what the modern state-of-the-art is but there’s a neat approach called “quadtree decomposition” where the matrices are recursively subdivided into quadrants in such a way that reuse is near-optimal for all of the levels of cache. Automatically, without knowing the cache characeristics ahead of time. Older approaches used implementations where the sub-blocks were hand-optimized for each machine’s cache architecture. https://dl.acm.org/doi/10.1145/781498.781525
And it’s not just textbook algorithms like matrix multiply that can exploit locality to reuse cached values…things like weather simulation often can be dcomposed in the same way, so that local interactions are modeled at a fine level with a minimum of communication to other cores / chips / RAM / etc.
I suspect your maths is out. There are 46 thousand LX2 CPU’s with 304 ARMv9 cores. Each LX2 is capable of 159 gigaflops.
Which is 13.8 million ARMv9 cores.
If you assume a theoretical maximum of 8 double-precision floating-point operations per clock cycle, at 1.55 GHz that is:
8 x 1.55g x13.8m ~= 171.12 exaflops if all memory access were register only. That is far from reality.
159g × 46 k ~= 7.314 exaflops if all memory accesses were L1 and L2 caches and high bandwith memory only..
That is still far from reality, but it is getting closer to the 2.2 exaflops that would be possible with DDR5 memory accesses.
Check your prefixes. Your math is out by a factor of 1000.
TFA states max throughput is 2.736 exaflops.
https://en.wikipedia.org/wiki/LineShine seems to have distilled it correctly.
Each of the ~45k LX2 CPUs has two dies.
Each die has 4 domains.
Each domain has 38 cores and 4 GB of high bandwidth memory, plus 32 GB of DDR5 DRAM.
So each CPU package has the 304 cores, 32 GB of HBM and 256 GB of DRAM.
From context, then, each core is itself massively parallel, able to perform 128 floating point operations in a single cycle, (but presumably only to its tightly-coupled local HBM).
And each package sucks a few hundred watts. The images shared at ISC 2026 this week imply the CPU packages are water cooled, though it’s not obvious where the plumbing goes.
Did you multiply the numbers and then shift the decimal place ?
Because I can not see anything wrong with my ballpark maths.
Giga = 10^9 Mega = 10^6 G * M = 10^15, i.e. Peta. Exa = 10^18
https://www.quickanddirtytips.com/articles/math-or-maths/
“Maths” is one of those midwit things that people assume is grammatically correct but in fact that is the one that originates from a misunderstanding.
You also don’t pluralize the short version of “economics” for some reason. It’s econ 101, not econs 101. Economics isn’t a plural noun… it’s not a collection of singular “economic” in a group, rather the s is added to create a (singular) noun from the word economic.
Also the abbreviation “math” was used first in the 19th century. In America. We invented it actually.
Vector operations and matrix math. Most of the operations will be multiply-accumulate, possibly counted as 2 operations, and the results stored back to the same register. Heavy pipelining, possibly staged on each clock edge. Large register banks, so intermediate data never even goes to L1 cache. In short, massive parallelism per core.
Lineshine: 53 Gflops/W
Compare to AMD 9980X: 64 cores, 350 W, 555 Gflops
Per core: 5.5 W, 8.67 Gflops, 1.57 Gflops/W
Compare to AMD 9955HX3D 16 cores, 55 W, 144 Gflops
Per core: 3.4 W, 9 Gflops, 2.64 Gflops/W
Comparing Lineshine to AMD modern: 20 to 33.7 times as efficient. Still impressive.
Keep in mind that Lineshine clock, 1.55 GHz, is less than half the 9980X’s 3.2 GHz and less than 29% of the 9980X’s 5.4 GHz Turbo Speed (which can’t be maintained indefinitely). That means that the Lineshine will be running on a much lower voltage, probably doubling efficiency. Also, ARM is more efficient than X86. Lineshine is likely purpose-built for programs that will also score well in floating-point tests.
Still impressive.
The quoted number will be peak performance. I/O limitations will likely be extreme. On the other hand, nuclear and chemical simulations will likely stay in-core for a relatively long time, until something says “BOOM” or a deadlier COVID is invented.
Whoa, we can say it was invented now? Neat
Does a supercomputer somehow cease to be a supercomputer as time passes? If you think so, then I wonder what kind of criteria decides that. If you think not, then you realize that my idea of supercomputer could be different from yours, and if something is amazingly performant to me, why shouldn’t I consider it a supercomputer?
A Raspberry Pi Zero is pretty darned close in raw performance to a Cray 1. While I’m not running the same kind of applications on a Pi Zero as were run on a Cray 1, it still feels like magic that I can run code at 100 MFLOPS any time I want.
Something of this scale seems like a situation where the interconnect is a lot more interesting than the CPUs themselves. Unfortunately details on this ‘LingQi’ seem to be fairly sparse.
Also, I assume that this makes sense for the intended application; but does the amount of RAM surprise anyone else? HBM for CPUs should be fairly speedy; but a total of only 36GB per 304 cores is a RAM/core ratio that’s radically lower than on a more ‘typical’ system
Read it more carefully. It’s 36 GB per domain of 38 cores. Eight domains with a total of 288 GB make up the 304-core CPU.