softcore

4 Articles

Bit-Serial CPU: Ultra-Tiny VHDL-Based CPU With Forth Interpreter

February 24, 2024 by 11 Comments

Soft cores for FPGAs come in many different flavors, covering a wide range of applications. The Bit-Serial CPU (bcpu) soft core presented by [Richard James Howe] is interesting for taking up just about the most minimal amount of resources (23 slices, 76 LUTs) while providing the means to run a Forth-based (eForth dialect) interpreter. To this CPU core a UART can be added (92 LUTs), as well as other peripherals.

As [Richard] states, the entire core with UART fits in 73 slices (220 LUTs) on a Spartan 6, while requiring a single port BRAM (block RAM). It features a 16-bit accumulator and lacks features such as interrupts, byte addressability and function calls, but those are not required to run the eForth interpreter. The main purpose of this soft core (other than the challenge) is to have a UART-programmable core that can be slotted in any FPGA design. For more serious requirements [Richard] also has the H2 SoC, which can run full-fat FORTH.

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IBM Reveals POWER10 CPU Based On The OpenPOWER ISA 3.1 Specification

August 19, 2020 by 22 Comments

This week, IBM revealed their POWER10 CPU, which may not seem too exciting since it’s primarily aimed at big iron like mainframes and servers. The real news for most is that it is the first processor to be released that is based on the open Power ISA specification v3.1. This new version of the Power ISA adds a number of new instructions as well as the notion of optionality. It updates the v3.0 specification that was released in 2015, right after the founding of the OpenPOWER Foundation.

Currently, a number of open source designs for the Power ISA exists, including MicroWatt (Power v3.0, VHDL) and the similar ChiselWatt (written in Scala-based Chisel).  In June of this year, IBM also released the VHDL code for the IBM A2 processor on Github. This is a multi-core capable, 4-way multithreaded 64-bit design, with silicon-implementations running at up to 2.3 GHz and using the Power ISA v2.06 specification.

The ISA specifications and other relevant technical documentation can be obtained from the OpenPOWER website, such as for example the Power ISA v3.0B specification from 2017. The website also lists the current cores and communities around the Power ISA.

(Main image: POWER10 CPU, credit IBM)

SoftCore CPU Comparison

July 12, 2020 by 19 Comments

Monty Python once did a sketch where people tried to summarize Proust in fifteen seconds. Although summarizing eight FPGA-based CPUs is almost as daunting, [jaeblog] does a nice job of giving a quick sketch of how the CPUs work with the Xilinx Vivado toolchain and the Digilent Arty board.

The eight CPUs are:   VexRiscv, LEON3, PicoRV32, Neo430, ZPU, Microwatt, S1 Core, and Swerv EH1.

The comparison criteria were very practical: A C compiler (gcc or llvm) for each CPU and no CPUs that were tied to a particular FPGA. Two of the CPUs didn’t fit on the Arty board, so their comparisons are a bit more theoretical.  There were other considerations such as speed, documentation, debugging support, and others.

It was interesting to see the various CPUs ranging from some very mature processors to some new kids on the block, and while the evaluations were somewhat subjective, they seemed fair and representative of the things you’d look for yourself. You can also get the test code if you want to try things for yourself.

The winner? The post identifies three CPUs that were probably the top choices, although none were just perfect. Of course, your experience may vary.

If you want an easy introduction to adding things to a soft CPU, this RISC-V project is approachable. Or if you prefer SPARC, check out this project.

Introducing The FleaFPGA Experimenter’s Board

February 14, 2014 by 48 Comments

[Valentin] recently tipped us about an FPGA development board he just finished. It is called the FleaFPGA and is aimed to get people interested in the world of Field Programmable Gate Arrays. One of the other reasons that also got [Valentin] to design his own board was that he was frustrated with the existing solutions, them being either too pricey or fairly spare in terms of connectivity.

The main components that you can see in the platform shown above are: a lattice MachX02-7000HE FPGA (6864LUTs), 256Mbits of SDRAM, a USB2.0 host port, a 4096-color VGA connector, a 3.5mm stereo connector, an SD/MMC card slot, a PS/2 keyboard/mouse combo port, a few push buttons and LEDs. An expansion header is also present in order to connect the FleaFPGA to future shields that will be developed. Unfortunately only the board schematics have been released and [Valentin] is currently aiming for a price of $60 per board for <100 quantities. You’ll be able to see a video of the board in action after the break, in which the FPGA has been loaded with a 68000 software core running a variation of the Amiga Juggler Demo.

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