Arm Gives Gift To Startups: Zero Cost

Who hasn’t dreamed of pulling together some gadget in their garage and turning it into a big business? Of course, most gadgets today have a CPU in them, and Arm CPUs power just about any kind of embedded device you can think of. If you just want to use a chip, that’s easy. You buy them from a licensee and you use their tools for development. But if you want to integrate ARM’s devices into your own chips, that’s a different story. You have to pay fees, buy tools, and pay licenses on each chip you produce. Until now. Arm’s flexible access for startups program will let you apply to get all of that free.

To qualify, you have to be an “early stage silicon startup with limited funding.” Normally, flexible access costs about $75,000 to $200,000 a year and that doesn’t cover your license fees and royalties. The plan offered to qualifying startups is the $75,000 package, but that still includes access to nearly all Arm products, technical support, a few introductory training credits, and development tools. After your first tape-out, though, it looks as though you’ll have to pony up.

Granted, we aren’t sure how many people are going to start a fabless silicon startup, but if you are, this is pretty big news. Not only is it a big cost savings, but you can do things that would be hard to do without this level of access. For example, it would be easy to try one CPU core and then decide later go to a larger or smaller CPU since you have access to nearly all the product lines.

We can’t help but think, though, that this is probably in response from pressure from the open source CPU movement. Of course, it makes sense for Arm, too. They want to make their money from royalties on things that sell hundreds of thousands, not from your dorm room prototype.

So you can take your pick, get started with Arm for free and pay later, or pick up RISC V and see how far that takes you. This project might give you some RISC V inspiration.

24 thoughts on “Arm Gives Gift To Startups: Zero Cost

      1. That’s because the Vector-V open stereo-GPU module integration is not public yet.
        Both ARM64 and NVIDIA hear the footsteps of a new giant in the distance with register level dual-ported memory access, and a full regression tested rendering pipeline. The Media codecs are still not free though… meh… I’d wait anyway given most of ARM’s advanced features are turned off by default in order to get a reliable OS.

        My toys are better than yours… I’d still use the 8086 or 6502 core if I could. =P

        1. I’m trying to picture a modern day 4GHz 6502 cycling through it’s 16-bit address space (64KiB) or the a modern 8086 cycling through its 20-bit address space (1MiB).

          Either CPU would need some major tweaks to their ISA to be able to “just” display web pages (Some pages can use nearly half a megabyte or more on a single animated image I’ve even seen others on this site in the past that used 22 MiB on an animated image ).

          And I agree ARM are fearful of RISC-V. If RISC-V should be able to work well in the server space, mobile space and embedded space. A lot of the design decisions are

          The above move to me is that ARM holdings want people to invest large chunks of time into using ARM, that psychologically makes it harder to do a full u-turn at a later date to go design a different non-ARM core. At this exact moment in time ARM has more spit and polish on their product, but they have made at least one bad decision in ARM v8, it does not include a compressed instruction format.

          1. Sorry I clicked on post without reading it back first and left half a sentence hanging

            …. A lot of the design decisions are genius in RISC-V, anyone who has read “The RISC-V Instruction Set Manual”, where they point out why the decisions were made, will be impressed.

          2. No. ARMv8 instructions are just better suited for high performance CPUs.

            There is no genius in RISC-V, it’s just optimised for trivial implementations (2R1W instructions, …), and it’s very conservative (no new idea).

          3. @TREZA So using less bandwidth, when possible, between the RAM and CPU, and using less space in the valuable CPU caches, so that more instructions can be cached, would somehow negatively effect performance ?

          4. @TREZA
            > It’s very conservative (no new idea).
            I fully agree with you, but they are not trying to make big innovations, just an open royalty free easy to implement ISA. Cherry picking the best from past designs, I’m guessing mostly from expired patents.

            It is not they are trying to innovate on multiple fronts in parallel like the Mill architecture ( ) which, can on paper, decode and issue up to 30 opcodes per cycle.

          1. I can’t comment at a deeper level, but to the people replying to this comment, and anyone else who hasn’t heard, the ESP32-S2 has a RISC-V coprocessor in it.

      2. Sorry but it’s already matter. There is quite a few product embedding risc-v cores, albeit not advertised as they are mostly “internal” cores not available to the user.
        Not even counting western digital drives that now embed them.

      3. RISC-V is not a joke.
        RISC-V is real.
        It may well be 10 years or more before RISC-V will be the latest and greatest processor, but for now there is plenty of work going on in the low-end stuff. The market where billions of uC’s are churned out each year.

        For some time there is the Sipeed Longan Nano – RISC-V GD32VF103CBT6 and now also a brand new competitor with the latest Espressiv board presented here on Hackaday.

        And I’m fairly certain that RISC-V is the cause of this change in the way ARM behaves, and ARM may well succeed in postponing the growth of RISC-V for a few years.

        At the moment were still at the beginning of an (possibly?) exponential curve.

  1. I am having flashbacks to 1996 — Hey, can anyone tell me where my “Power PC motherboard reference EVB” is??? I cant wait to get started with this power PC architecture, it surely will be the death of X86

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