Spade is an open-source hardware description language (HDL) developed at Linköping University, Sweden.
Other HDLs you might have heard of include Verilog and VHDL. Hardware engineers use HDLs to define hardware which can be rendered in silicon. Hardware defined in HDLs might look like software, but actually it’s not software, it’s hardware description. This hardware can be realized myriad ways including in an FPGA or with an ASIC.
You have probably heard that your CPU processes instructions in a pipeline. Spade has first-class support for such pipelines. This means that design activities such as re-timing and re-pipelining are much easier than in other HDLs where the designer has to implement these by hand. (Note: backward justification is NP-hard, we’re not sure how Spade supports this, if it does at all. If you know please enlighten us in the comments!)
Spade implements a type system for strong and static typing inspired by the Rust programming language and can do type inference. It supports pattern matching such as you might see in a typical functional programming language. It boasts having user-friendly and helpful error messages and tooling.
Spade is a work in progress so please expect missing features and breaking changes. The documentation is in The Spade Book. If you’re interested you can follow development on GitLab or Discord.
So now that you know about the Spade language, are you planning to take it for a spin? You will find plenty of Verilog/VHDL designs at Hackaday which you could re-implement using Spade, such as an easy one like Breathing LED Done With Raw Logic Synthesized From A Verilog Design (see benchmarks) or a much more challenging one like Game Boy Recreated In Verilog. If you give Spade a go we’d love to see what you come up with!
please make a cpu https://tic80.com/ and gpu, sound accelarators.
simple computer, many program for testing and one battery for a working demo for whole week.
Very cool, the HDL scene can use some shaking up. Haven’t written any VHDL recently but can remember how painful and verbose pipelines are, this seems like a big improvement!
Verilog is more like C. Never had any trouble learning it. Only possible complaint is that synthesizable Verilog is a subset of the language, and you need to be careful how you write code that you are going to synthesize so you don’t get massive extra hardware.
Synthesisable code is always a subset, because an HDL without a way to generate testbenches etc is pretty useless.
Exactly. Takes a little getting used to, but I loved doing Verilog designs because I could mock up a solution, test it and then compile and simulate.
Hi, Spade author here! Spade is a synthesis only language (well, apart from a simple assert construct) with testbenches being written primarily in https://www.cocotb.org/ giving the full power of python to testbench development.
I think a big reason VHDL and Verilog are hard to pick up for beginners is that it is extremely unclear what is and isn’t synthesizeable, and if you have an architecture in mind, it is often hard for students to know how to express that.
In many ways, I think the languages try to be both synthesis and simulation languages and end up being bad at both.
Spade author here! Verilog being like C is quite an apt comparison in my opinion. If you want full control, over all the details, C and Verilog will certainly give you that, but at the cost of very little abstraction. Verilog complicates things by the synthesizeable subset where you aren’t really sure what you get, but still…
Spade aims to be the Rust or maybe C++ of the HDL world where you can work at a higher abstraction level when convenient, but still write things at the pure RTL level when needed for performance.
I’ll admit that my professional time with VHDL has been limited, and I’ve always been interested in the “cutting edge” of new tech.
But after seeing the way this guy writes VHDL (https://hardwaredescriptions.com/conquer-the-divide/) I’ve reconsidered the trend of using Scala, Python, etc. as a HLS language that “complies” to verilog.
Maybe we should focus on using and extending the HDLs we already have (or maybe changing the radification process and/or incentivicizing tool makers to be compliant to the latest standards)
Spade author here, Fun to see Spade make its way onto hackaday!
I suppose I’m qualified to answer this :D
Spade does not actually do any retiming on its own, it just gives you syntactic sugar to do it yourself in a way that doesn’t require manually managing all your registers. If you have pure pipelines with no feedback, you can be sure that if you retime a circuit and it compiles again, the output will be the same (apart from different latency of course). If you have feedback, you loose that correctness guarantee but still have the syntactic advantages of being able to reason in terms of pipeline stages instead of individual registers.
Automatic retiming would be very interesting to explore in the future, though even then it’d probably only be done in the absence of feedback. If you want something right now https://github.com/JulianKemmerer/PipelineC is another HDL which does do automatic pipelining.
Thanks for this explanation! And thanks also for making Spade, it is very impressive technology. I wish you every success with it!
Pipelining can be done well in Verilog but you have to be fastidious, and most people aren’t. In all of my modules I usually have a sections called “delay lines” which sets up delay lines for inputs, flags, and some intermediate results, and another section called “latency parameters”. Then you can have code like this:
if (data_vld_dly[SORTER_LATENCY]) adder_out <= sorter_out + 5;
if (data_vld_dly[SORTER_LATENCY+ADDER_LATENCY])
mult_out <= data_in_dly([SORTER_LATENCY+ADDER_LATENCY] * adder_out);
This isn’t a useful example but you can see how there are several pipeline stages. If the place & route guys tell you that the sorter isn’t meeting timing, you can add a pipeline stage to the sorter, increase SORT_LATENCY by 1, and everything is automatically adjusted.
Compatibility? For someone who’s only knowledge of FPGAs is what they are (like a microcontroller which I’ve used loads, but unlike a microcontrolelr you set up circuits of logic gates rather than sequentially performed lines of code), and has long wanted to get in to programming them but not until there’s a good linux toolchain which isn’t dependent on proprietary subscription services and software which checks with webservers before it will start… What is the hardware compatibility like for Spade? Which FPGA types can it compile for? How is the compilation and flashing to a particular FPGA dev board done in practice? I couldn;t find anything in the Spade docs website about this. Thanks
Spade generates Verilog which is is read by pretty much any FPGA or ASIC tools. It also has pretty good interoperability with verilog if you want to mix and match the two.
The docs not mentioning anything about board support is a good point. Generally, the Spade build system works best with open source supported FPGAs which in practice means ice40, ecp5, or gowin FPGAs.
We have some templates set up for some boards here https://gitlab.com/spade-lang/swim-templates, if your FPGA is on that list you can go from nothing to blinking LEDs in 4 commands
install rust
install swim (the spade build system)
create a new project from a template
compile, synthesize and upload
If your board is not on the list, you can copy an existing one and modify it as needed as long as it has an FPGA in one of the three families mentioned previously
I thought we had a docs page about this but it looks like we don’t, I’ll add one today!
I don’t think Spade does it (Google’s XLS does; I worked on it), but ASIC retiming can be done efficiently using the algorithm in “SDC-Based Modulo Scheduling for Pipeline Synthesis”. If you want to apply that to general RTL (rather than a pipeline with feedback), you need to solve the minimum feedback arc set problem, which is indeed NP complete, but in practice is easy to approximate because ASIC designs have sparse connectivity.
Check out XLS, which also gives you an intermediate representation which can be executed with a JIT and focuses on a similar retiming idea.
https://youtu.be/TOJ8QWuEec8
Theirs also renderers down to a few of the “open” process design kits (at least in the colab notebook 😆)