Behind The Scenes Of The 2019 Superconference Badge

November 16, 2019 by Tom Nardi 7 Comments

If you count yourself among the several hundred of our closest friends that have joined us at Supplyframe HQ for the 2019 Hackaday Superconference, then by now you’ll have your hands on one of this year’s incredible FPGA badges. It should come as no surprise that an incredible amount of time and effort went into developing and manufacturing this exceptionally unique piece of hardware; the slick gadget in your hands today took nearly an entire year to develop, and work continued on it until very literally the last possible moment.

Badge designer Jeroen Domburg (aka Sprite_TM), Hackaday staff, and a team of dedicated volunteers were still putting the final touches on these ambitious devices less than 24 hours before they were distributed to the first wave of Superconference attendees. Naturally, that’s not exactly how things were supposed to go. But when you’ve got a group of people that want to push the envelope and build something truly incredible, convincing them to actually stop working can be a challenge in itself.

In fact, development of the badge is still ongoing. Fixes and improvements are being made to the software even as you read this, and if you haven’t already, you should upgrade your badge to make sure you’ve got the latest and greatest from our international team of wizards. We all know that conference badges have an unfortunate habit of languishing on the shelf and collecting dust, but the 2019 Superconference badge was built to challenge you for longer than just one weekend. Consider yourself warned: for every Supercon badge that gets tossed in a drawer come Monday, Sprite_TM will shed a single tear.

After the break, come along as we turn back the clock and take a look at the last minute dash to get 500+ badges programmed and ready to go before the doors opened for the 2019 Hackaday Superconference.

Continue reading “Behind The Scenes Of The 2019 Superconference Badge” →

Speeding Up IOTA Proof Of Work Using FPGAs

November 16, 2019 by Sharon Lin 5 Comments

Blockchain has existed as a concept since the early 1990s, but keeping a distributed ledger for IoT transactions wasn’t widely implemented until IOTA developed Tangle. The blockchain company was initially founded as a hardware startup and pivoted to work on transactional settlement for IoT. The Tangle, their distributed ledger architecture based on a directed acyclic graph (DAG) works as a “blockchain without the blocks and the chain”.

As its name implies, the Tangle is a web of transactions that references its past two transactions and a subsection of other transactions. Rather than miners and stakers being responsible for overall consensus, all active participants are involved in the approval of transactions. The transaction process requires the client to sign with their private keys, select two random unconfirmed transactions to be referenced, and perform proof-of-work.

The proof-of-work has an unfortunately high difficulty as you might expect. The process is similar to finding a nonce in Bitcoin mining, although the difficulty is set at a lower threshold due to the transactions running on lower-power nodes. Even so, since IOTA transactions commonly occur on small embedded platforms this can take several minutes to complete, a relatively long time considering these are mere transactions.

Since Curl-P81 hashes should be computed in parallel, they can’t be computed efficiently on general purpose CPUs. The PiDiver 1.3, [Thomas Pototschnig]’s port of the IOTA Reference Implementation (IRI) PearlDiver, performs searches for nonces. Because it runs on FPGAs, it is able to speed up the proof-of-work by a factor of more than 140 when compared to a Raspberry Pi. The FPGA is able to calculate one round of the hash in a single clock cycle, and a complete hash in 85 cycles (as well as testing for a valid nonce). Seven parallel hashes can be calculated at once, giving 15.8MHash/s at a frequency of 188MHz. The proof-of-work takes ~300ms on the FPGA when compared to 90s on a Raspberry Pi, so this is a significant improvement in speed.

Since the project is open source, the core can be used by IRI for creating a modified version of their PearlDiver. The board can be used as a Raspberry Pi HAT, although it can also be connected via USB to work without the Pi.

While this doesn’t address the security concerns of using IOTA with personal IoT devices, it is certainly a significant improvement on the speed of their proof-of-work process, and the software speedup is incredibly satisfying to watch.

Continue reading “Speeding Up IOTA Proof Of Work Using FPGAs” →

Two Vintage Calculators In One

November 13, 2019 by Bryan Cockfield 10 Comments

The FPGA revolution that occurred within the past few decades was a boon to many people interested in “antique” electronics. The devices “wire together” logic elements as needed rather than emulating chips completely in a software layer, which makes them uniquely suited for replicating chips that are rare, no longer in production, damaged, or otherwise lost. They also make it easy to experiment with hardware, like this project which combines two antique calculators into one single unit.

The two calculators used in this combination device are the TI Datamath and the Sinclair Scientific, both released in the early 1970s, the former of which has been extensively documented and reverse engineered on at least one occasion. The reproduction from [zpekic] has a toggle that allows the user to switch between the two “modes”. This showcases the power of microprogramming and microcode, and of the FPGA platform itself. Although both modes are functional, there are still a few bugs resulting from how different the two pieces of hardware were, which is really more of an interesting facet of this project than anything.

The build is a great showcase of FPGA technology, not to mention a great read-through for understanding these two calculators and their fundamental differences in data entry and manipulation, clock cycles, memory, and everything in between. It’s worth checking out, even if you don’t plan on using a decades-old calculator in your day-to-day life.

Gigantic FPGA In A Game Boy Form Factor, 2019 Supercon Badge Is A Hardware Siren Song

November 4, 2019 by Mike Szczys 54 Comments

Look upon this conference badge and kiss your free time goodbye. The 2019 Hackaday Superconference badge is an ECP5 FPGA running a RISC-V core in a Game Boy form factor complete with cartridge slot that is more open than anything we’ve ever seen before: multiple open-source CPU designs were embedded in an open system, developed using the cutting-edge in open-source FPGA tools, and running (naturally) open-source software on top. It’s a 3,000-in-one activity kit for hardware people, software people, and everyone in between.

The brainchild of Jeroen Domburg (aka Sprite_TM), this design has been in the works since the beginning of this year. For more than 500 people headed to Supercon next week, this is a source of both geeky entertainment and learning for three action-packed days and well beyond. Let’s take a look at what’s on the badge, what you need to know to hack it, and how the design serves as a powerful development tool long after the badge hacking ceremonies have wrapped up.

Continue reading “Gigantic FPGA In A Game Boy Form Factor, 2019 Supercon Badge Is A Hardware Siren Song” →

The $5 FPGA

November 3, 2019 by Al Williams 60 Comments

You ever wonder exactly what’s inside that cheap stuff you get from China? Sometimes it is cheap parts you’ve never heard about. Case in point: if you are willing to import, you can score an FPGA board for about $5. The downside? You’ve probably never heard of the GOWIN Semi GW1N — one of the Little Bee FPGAs — that’s onboard.

There is some English documentation which leaves room for interpretation and you’ll have to use their IDE. Then again, it might be a fun puzzle to get one of these working. Looks like Seeed has them available for $4.90.

According to the Wiki, the onboard chip is GW1N-LV1QN48C6/I5, equipped with 1152 LUT4 logic resources, 1 PLL and a total of 72Kbit SRAM. The development board brings out all I/O interfaces. There’s also 64 Mbits of PSRAM. The board also has an RGB interface for a display, a 24 MHz clock, and the USB programming/debugging interface.

We didn’t try it, but the development tool looks to be available for Windows or Linux. Browsing through the wiki gives the impression it is usable, although probably simple — which could be an advantage compared to some other tool suites.

Worth a try? The Lattice chips are not that expensive and are well supported by open source tools. Then again, people want to try the very cheap (under a dime) CPU that is in a lot of products. So why not FPGAs, too?

SPARC CPU In A Cheap FPGA

November 1, 2019 by Al Williams 12 Comments

There was a time when SPARC CPUs were the sole realm of pricey Sun workstations, but now you can put one on an FPGA with just a little trouble. The problem is you need a fairly big FPGA which isn’t always cheap unless someone goes out of business and you get lucky. [Ttsiodras] picked up a Pano logic thin client. Pano went under and their entire inventory is out on the surplus market at cheap prices. With a little FPGA magic, you can turn a few bucks into a SPARC-based computer.

The insides of the workstation have a Spartan 6 FPGA inside and you’ll need to solder in some JTAG wires, but that shouldn’t put anybody here off. Of course, the Spartan 6 isn’t the newest tech so you’ll have to get an old version of the Xilinx tools but that’s not hard either. However, there is a strange irony you’ll need to be aware of if you use Linux.

Continue reading “SPARC CPU In A Cheap FPGA” →

FBus: An Extensible And Easily Configurable FPGA Based DAQ

November 1, 2019 by Gerrit Coetzee 4 Comments

[flow] is a little disillusioned with commercial Data Acquisition Systems (DAQs) and channeled his frustration into his own, very cool, FPGA based solution.

The project takes form as a back plane into which various cards can be slotted. The the interface is just a PCI-e connector. If you need analog input, simply insert the card for it. Ethernet output? Same process. Modularity and expandability are the themes here.

[flow] already has projects in mind for his new DAQ. He’s using it to build an inverted pendulum. However, his planned cards really show the possibilities, anything from a logic analyzer card to an HDMI Output card allow for a wide array of configurations. There is also a small suite of tools which makes this process relatively easy to manage.

We can definitely see this evolving into a useful tool on our bench for prototyping.