A Look At A Gaggle Of Transputer Boards

June 25, 2026 by Maya Posch 15 Comments

A long time before Beowulf clusters wired up with commodity Ethernet hardware became a hobbyist thing and a running joke, the transputer took a swing at a very similar architecture. This used stand-alone computers that were networked together with other transputer systems, to achieve task-level parallelism. For some people like [Lance Harvie] this is the kind of hardware that he used during his university years for a project, with him not only still having that hardware, but also recently adding to this collection with a recent eBay purchase.

The transputer story is a fascinating one, forming a major part of the UK’s semiconductor industry during the 1980s, creating a strong legacy as the computer industry awkwardly tried to figure out what types of parallelism to target. Whereas the industry largely moved to instruction-level (superscalar) parallelism alongside tightly coupled task-level parallelism along with multiple CPU cores on a single die, one could consider today’s supercomputer clusters to be one example of the transputer legacy.

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Putting A Teensy To Task As A Transputer Link

October 20, 2025 by Dave Rowntree 8 Comments

One downside of working with the old Inmos Transputer devices is the rarity and cost of the original silicon. Obviously, you can’t sidestep the acquisition of the processor—unless you emulate—but what about replacing the IMS C011/C012 link chip? You need this (expensive) part to interface the transputer to the programming host, but as [Erturk Kocalar] discovered, it’s perfectly possible to coax a Teensy to do that job for you just as well.

The unusual two-bit start sequence differentiates a data packet from an ACK. It’s simple to emulate if you use the LSB of a 9-bit word as a dummy start bit!

Transputers work by utilizing an array of bit serial interfaces to connect a network of devices, allowing for cooperative computation on tasks too large to fit on a single device. This protocol is, at its link level, a simple asynchronous bit serial affair, with 11-bit data messages, and a raw two-bit frame for the acknowledge. The C011 device at its heart is just a specialized UART—it takes 8-bit parallel data from the host, dealing with handshaking, and pushes it out to the first transputer in the chain at 5, 10 or 20 Mbps, but inverted and with two start bits and a single stop bit. In parallel, it performs the same task in the reverse direction.

[Erturk] realized that the Teensy UART has an inverted mode and, crucially, a 9-bit data mode. This allows the second start bit to be generated as bit 0 of the word, with the remaining eight bits forming the payload. Simple stuff. Additionally, the Teensy UART is capable of the maximum transputer bitrate of 20 Mbps, without breaking a sweat.

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Fancy Adding A Transputer Or Two To Your Atari ST?

May 14, 2025 by Dave Rowntree 9 Comments

Has anybody heard of the ATW800 transputer workstation? The one that used a modified Atari ST motherboard as a glorified I/O controller for a T-series transputer? No, we hadn’t either, but transputer superfan [Axel Muhr] has created the ATW800/2, an Atari Transputer card, the way it was meant to be.

The transputer was a neat idea when it was conceived in the 1980s. It was designed specifically for parallel and scientific computing and featured an innovative architecture and dedicated high-speed serial chip-to-chip networking. However, the development of more modern buses and general-purpose CPUs quickly made it a footnote in history. During the same period, a neat transputer-based parallel processing computer was created, which leveraged the Atari ST purely for its I/O. This was the curious ATW800 transputer workstation. That flopped as well, but [Axel] was enough of a fan to take that concept and run with it. This time, rather than using the Atari as a dumb I/O controller, the card is explicitly designed for the Mega-ST expansion bus. A second variant of the ATW800/2 is designed for the Atari VME bus used by the STe and TT models—yes, VME on an Atari—it was a thing.

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The Transputer In Your Browser

April 4, 2025 by Al Williams 13 Comments

We remember when the transputer first appeared. Everyone “knew” that it was going to take over everything. Of course, it didn’t. But [Oscar Toledo G.] gives us a taste of what life could have been like with a JavaScript emulator for the transputer, you can try in your browser.

If you don’t recall, the transputer was a groundbreaking CPU architecture made for parallel processing. Instead of giant, powerful CPUs, the transputer had many simple CPUs and a way to chain them all together. Sounds great, but didn’t quite make it. However, you can see the transputer’s influence on CPUs even today.

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Raspberry Pi Pico Used As A Transputer

August 5, 2021 by Mike Szczys 43 Comments

You can’t fake that feeling when a $4 microcontroller dev board can stand in as cutting-edge 1980s technology. Such is the case with the working transputer that [Amen] has built using a Raspberry Pi Pico.

For a thorough overview of the transputer you should check out [Jenny List’s] longer article on the topic but boiled down we’re talking about a chip architecture mostly forgotten in time. Targetting parallel computing, each transputer chip has four serial communication links for connecting to other transputers. [Amen] has wanted to play with the architecture since its inception. It was expensive back then and today, finding multiple transputers is both difficult and costly. However, the RP2040 chip found on the Raspberry Pi Pico struck him as the perfect way to emulate the transputer design.

The RP2040 chip on the Pico board has two programmable input/output blocks (PIOs), each with four state machines in them. That matches up perfectly with the four transputer links (each is bi-directional so you need eight state machines). Furthermore, the link speed is spec’d at 10 MHz which is well within the Pico’s capabilities, and since the RP2040 runs at 133 MHz, it’s conceivable that an emulated core can get close to the 20 MHz top speed of the original transputers.

Bringing up the hardware has been a success. To see what’s actually going on, [Amen] sourced some link adapter chips (IMSC011), interfacing them through an Arduino Mega to a computer to use the keyboard and display. The transputer architecture allows code to be loaded via a ROM, or through the links. The latter is what’s running now. Future plans are to figure out a better system to compile code, as right now the only way is by running the original INMOS compiler on DOS in a VM.

Listen to [Amen] explain the project in the first of a (so far) six video series. You can find the links to the rest of those videos on his YouTube channel.

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Retrotechtacular: Transputer

April 19, 2019 by Jenny List 103 Comments

Back in 2016, Hackaday published a review of The National Museum of Computing, at Bletchley Park. It mentions among the fascinating array of computer artifacts on display a single box that could be found in the corner of a room alongside their Cray-1 supercomputer. This was a Transputer development system, and though its architecture is almost forgotten today there was a time when this British-developed microprocessor family had a real prospect of representing the future of computing. So what on earth was the Transputer, why was it special, and why don’t we have one on every desk in 2019?

An Inmos RAMDAC (the 28-pin DIP) on the motherboard of a 1989 IBM PS/55. Darklanlan [CC BY 4.0]

Inmos, based in Bristol, were a — no, make that the — British semiconductor company, in the days when governments saw such things as a home-grown semiconductor manufacturing capability to be of strategic importance. They made microcomputer peripheral chips, RAM chips, and video chips (the workaday silicon of 1980s computing) but their exciting project was the Transputer.

This microprocessor family addressed the speed bottlenecks inherent to conventional processors of the day by being built from the ground up to be massively multiprocessor. A network of Transputer processors would share a web of serial interconnects arranged in a crosspoint formation, allowing multiple of them to connect with each other independently and without collisions. It was the first to feature such an architecture, and at the time was seen as the Next Big Thing. All computers were going to use Transputers by the end of the 1990s, so electronic engineering students were taught all about them and encountered them in their group projects. I remember my year of third-year EE class would split into groups, each of tasked with a part of a greater project that would communicate through the crosspoint switch at the heart of one of the Transputer systems, though my recollection is that none of the groups went so far as to get anything to work. Still how this machine was designed is fun to look back on in modern times. Let’s dig in!

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