Since an FPGA is just a sea of digital logic components on a chip, it isn’t uncommon to build a CPU using at least part of the FPGA’s circuitry. VexRiscv is an implementation of the RISC-V CPU architecture using a language called SpinalHDL.
SpinalHDL is a high-level language conceptually similar to Verilog or VHDL and can compile to Verilog or VHDL, so it should be compatible with most tool chains. VexRiscv shows off well in this project since it is very modular. You can add instructions, an MMU, JTAG debugging, caches and more.
Continue reading “VexRiscv: A Modular RISC-V Implementation for FPGA”
Cornell Students [Sean Carroll], [Gulnar Mirza], and [James Talmage] designed a realtime pitch shifter to run on their DE1-SoC and controlled by its ARM core.
The team’s goals were to pitch-shift the left and right outputs independently, to produce chords using the original voices as well as the pitch-shifted ones, and time-delayed pitch shifting. All of it is controlled on a VGA monitor through a simple GUI, allowing users to create lots of different effects by layering the different options.
Under the hood they made use of dual circular buffers to do the pitch shifting, reading in the sample and then using simple fixed-point arithmetic to modify it, then running the signal through a Butterworth filter to clean up artifacts.
The project was built as part of [Bruce Land]’s ECE5760 class. If you’re looking for more DE1 goodness, you’ll find excellent projects aplenty on Hackaday, including the LED Matrix Audio Visualizer from last year and Synthesizing Strings on a Cyclone V, among many others.
Continue reading “Voice Shifting with a Cyclone V FPGA”
Years in the making, Apertus has released 25 beta developer kits for AXIOM–their open source digital cinema camera. This isn’t your point-and-shoot digital camera. The original proof of concept from 2013 had a Zynq processor (a Zedboard), a super 35 4K image sensor, and a Nikon F-Mount.
The device today is modular with several options. For example, there is an HDMI output module, but DisplayPort, 4K HDMI, and USB 3.0 options are in development. You can see several sample videos taken with the device, below.
Continue reading “Open Source Digital Cinema”
Reconfigure.io is accepting beta applications for its environment to configure FPGAs using Go. Yes, Go is a programming language, but the software converts code into FPGA constructs, so you don’t need Verilog or VHDL. Since Go supports concurrent routines and channels for synchronization and communications, the parallel nature of the FPGA should fit well.
According to the project’s website, the tool also allows you to reconfigure the FPGA on the fly using a cloud-based build and deploy system. There isn’t much detail yet, unless you get accepted for the alpha. They claim they’ll give priority to the most interesting use cases, so pitching your blinking LED project probably isn’t going to cut it. There is a bit more detail, however, on their GitHub site.
Continue reading “You are Go for FPGA!”
[Claire Chen] and [Mark Zhao], students in [Bruce Land]’s ECE5760 class at Cornell, created a project aimed at the manufacturing sector: quality-checking manufactured products automatically by visually scanning a bunch of them and processing the pixels one at a time. Ordinarily, the time when the widget comes off the line is when you have to bring in actual people to inspect. This project uses morphological image processing to like dilation and erosion to look for flaws.
[Claire] and [Mark] created a simulated manufacturing line with a servo-driven belt that brings a series of Spree candies into the range of a camera, which scans them. The SoC with a Cyclone V FPGA and ARM Cortex-9 then processes the raw images to establish the object’s color, while running it through a couple of algorithms to look for defects. The FPGA tracks how many Sprees that have passed by as well as their color, maintaining a 99% success rate with a rate of 5-10 frames per second. The FPGA also looks at each blob of color as a collection of pixels, establishing connectivity to help to distinguish multiple Sprees touching each other.
Also be sure to check out [Claire] and [Mark]’s bike sonar project from a previous semester.
Continue reading “Quality Assurance Through FPGA”
The human auditory system is a complex and wonderful thing. One of its most useful features is the ability to estimate the range and direction of sound sources – think of the way people instinctively turn when hearing a sudden loud noise. A team of students have leveraged this innate ability to produce a game of tag based around nothing but sound.
The game runs on two FPGAs, which handle the processing and communication required. The chaser is given a screen upon which they can see their own location and that of their prey. The target has no vision at all, and must rely on the sounds in their stereo headphones to detect the location of the chaser and evade them as long as possible.
The project documentation goes into great detail about the specifics of the implementation. The game relies on the use of the Head Related Transfer Function – a function related to how the ear picks up sounds relative to their position. This allows the FPGA to simulate the chaser’s footsteps, and feed the audio to the target who perceives the chaser’s position purely by sound.
It’s a great example of a gameplay mechanic that we’d love to see developed further. The concept of trying to find one’s way around by hearing alone is one which we think holds a lot of promise.
With plenty of processing power under the hood, FPGAs are a great choice for complex audio projects. A great project to try might be decoding MP3s.
[Bruce Land] is one of those rare individuals who has his own Hackaday tag. He and his students at Cornell have produced many projects over the years that have appeared on these pages, lately with FPGA-related projects. If you only know [Land] from projects, you are missing out. He posts lectures from many of his classes and recently added a series of new lectures about developing with a DE1 System on Chip (SoC) using an Altera Cyclone FPGA using Verilog. You can catch the ten lectures on YouTube.
The class material is different for 2017, so the content is fresh and relevant. The DE1-SOC has a dual ARM processor and boots Linux from an SD card. There are several labs and quite a bit of background material. The first lab involves driving a VGA monitor. Another is a hardware solver for ordinary differential equations.
Continue reading “An Education on SoC using Verilog”