Ask Hackaday: We Might Have Some FPGAs To Hack

January 11, 2013 by Brian Benchoff 79 Comments

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[Chris] is an IT guy for a medical clinic up in Alaska, and until very recently the systems he monitored, fixed, and beat with a wrench included over 100 Pano Logic “Zero Client” thin clients. Pano Logic just went out of business and all support for these little boxes have been cut off, leaving [Chris] with a hundred or so very interesting pieces of hardware.

The idea behind these “zero clients” is the ideal of a thin client – take all the storage, processing, RAM, and other goodies and move them to a server. Pano Logic took this one step further than other thin clients, removing the CPU, memory, and basically everything you’d find in a thin client. What was left was a Spartan-6 FPGA, a few chips to drive the USB ports, a pair of HDMI chips, and a few DDR2 modules. Basically, [Chris] has about 150 FPGA dev boards just sitting in a storage room. The only thing that is needed is a bunch of software and an extreme amount of cleverness.

After opening one of these zero clients, [Chris] found a Spartan-6 FPGA right next to what he thinks is a 6-pin programming port. Along with the FPGA are a few other chips that would make any FPGA dev board a very neat tool:

We’re going to agree with [Chris] these Pano Logic zero clients show a lot of potential. If you’re up to the challenge of creating a very, very cheap FPGA dev board out of some discarded hardware, head on over to ebay or chat up your local IT guy.

UPDATE: Roll Your Own GPS Can Now Track Twice As Many Satellites

December 24, 2012 by Mike Szczys 31 Comments

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[Andrew Holme] wrote in to tell us about some work he’s done to improve his scratch-built GPS receiver. He figured out a way to use the same hardware but double the number of satellites it can track to a total of eight. When we looked at the original hardware about a year ago it was limited to monitoring just four satellites. That’s the bare minimum for calculating position data. This will not only help increase the accuracy, but remove the problems that would have been cause if just one satellite was dropped because of an obstruction or other issue.

His solution is based entirely on using the FPGA in a different way. He had taken up almost all of the gates available in the Xilinx Spartan 3 chip. Now he’s implemented a CPU on the chip and is able take some of the work off of the hardware gate design by running code on it. He also found and squashed a bug in how the data was processed. He says his original work wasn’t taking into account the rotation of the earth when determining position. All of these improvements put his accuracy at +/- five meters even when he’s not tracking all eight satellites!

Two Computer Vision Builds From Cornell

December 20, 2012 by Brian Benchoff 6 Comments

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[Bruce Land], professor at Cornell, is a frequent submitter to our tip line. Usually he sends in a few links every semester from undergraduate electronics courses. Now the fall semester is finally over and it’s time to move on to the more ambitious master’s projects.

First up is a head-mounted eye tracker, [Anil Ram Viswanathan] and [Zelan Xiao] put together a lightweight and low-cost eye tracking project that will record where the user is looking.

The eye tracker hardware is made of two cameras mounted on a helmet. The first camera faces forward, looking at the same thing the user is. The second camera is directed towards the user’s eye. A series of algorithms detect the iris of the user’s eye and overlays the expected gaze position on the output of the first camera. Here’s the design report. PDF, natch.

Next up is a face tracking project implemented on an FPGA. This project started out as a software implementation of a face tracking algorithm in MATLAB. [Thu-Thao Nguyen] translated this MATLAB code to Verilog and eventually got her hardware running on an FPGA dev board. Another design report.

Having a face detection and tracking system running on an FPGA is extremely interesting; the FPGA makes face tracking a very low power and hopefully lower-cost solution, allowing it to be used in portable and consumer devices.

You can check out the videos for these projects after the break.

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Breadboard Friendly FPGAs

December 11, 2012 by Brian Benchoff 57 Comments

Regular Hackaday readers will be familiar with all the cool things you can do with FPGAs; emulating old video game consoles, cracking encryption protocols, and DIY logic analyzers become relatively simple projects with even a modest FPGA dev board on your workbench. Many FPGA boards aren’t geared towards prototyping, though, and breadboard friendly devices are hard to come by. Here’s a pair of breadboardable FPGAs we’ve found while searching for some related hardware over the past few days

First up is the Mercury FPGA Module. Packaged in a DIP-64 format, the Mercury features a Spartan-3A FPGA with the equivalent of 200k logic gates. Elsewhere on the board is 512kB of RAM and 128kB of Flash storage. There are enough GPIO pins for nearly any project, but sadly only a 10-bit ADC – the same resolution you’d find in an AVR or PIC ‘micro.

Of course the Mercury isn’t the only breadboard-friendly FPGA dev board out there. There’s also the slightly more capable XuLA2 board powered by a Spartan-6 with 32 MB of RAM, 1MB of Flash. Unlike the Mercury, the XuLA2 can also fit in one of those ‘half-sized’ solderless breadboards.

Yes, it’s a different form factor than the commonly recommended Papilio One or the DE0. If you can suggest any other ‘beginners’ (i.e. doesn’t cost an arm and a leg) FPGA boards, leave a note in the comments and we’ll summarize them in another post.

Building A 100 MHz Frequency Counter

November 2, 2012 by Mike Szczys 5 Comments

The great thing about building with gates is the crazy speeds you can achieve by using hardware directly (as opposed to working with simple microcontrollers). This 100 MHz frequency counter is a great example. [Michael] just finished building it using a Papilio board.

Of course we’re not talking about discreet chips here. The Papilio is an FPGA development board which means he is building with hardware gates, but that is still done by writing code. Above, the rig is measuring a 25 MHz being generated by a second FPGA board. Using the Papilio’s on board 32 MHz clock the device is capable of counting a frequency up to 100 MHz. You can see it measuring a 96.875 MHz signal in the video after the break. One interesting thing about that clip is that near the end he touches the crystal’s case with his finger and the Hertz really jump for a moment.

If the 8-digit display looks familiar that’s because [Michael] recently published a library to use it with an FPGA.

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Discrete FPGA Will Probably Win The 7400 Logic Competition

November 1, 2012 by Brian Benchoff 19 Comments

For this year’s 7400 logic competition, [Nick] decided to build an FPGA out of logic chips (Internet Archive cached version).

Perhaps a short explanation is in order to fully appreciate [Nick]’s work. The basic component of an FPGA is a slice, or cell, that performs boolean operations on its input and sends the result on its output. The core of these slices is a lookup table – basically a truth table that stores the result of every possible input combination.

One very easy way to implement a lookup table is to use a RAM or EEPROM chip. By tying the address lines of an EEPROM to the input and the data lines to the output, it’s possible to create a single slice of an FPGA very easily.

Unfortunately for [Nick], 74-series memories have long been out of production. There is another option open, though: shift registers. A shift register is basically an 8-bit memory chip with parallel inputs, so combining a shift register with an 8-input multiplexer is a very simple way to implement a 3-input, 1-output FPGA slice.

After figuring out how to tie these slices to bus lines, [Nick] needed a way to program them. Verilog or VHDL would border on insanity, so he wrote his own hardware description language. It’s certainly not as powerful or capable as the mainstream solutions to programming an FPGA, but it’s more than enough.

In the video after the break, you can see [Nick]’s overview of his very large 8-slice FPGA while he runs a combination lock and PWM program. All the code, schematics, and board layout are up on [Nick]’s git if you’d like to build your own.
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Bora Board Teaches Binary Hardware

October 29, 2012 by Brian Benchoff 7 Comments

If you’re just starting out in your quest to build really cool electronic devices, you’ll find a ton of options ready for the beginner. The Arduino makes toggling pins dead simple, and the Raspi brings the wonders of blinking a LED from the command line down from the gods and into the hands of the common man. These are all software platforms, though, and if you want to learn digital logic with hardware the best option is still a drawer full of 7400-series logic chips.

[Colin O’Flynn] hopes to change this with a beginners board for digital logic hardware design. It’s called the BORA, or Binary explORer boArd, and brings digital logic to a convenient package that is far less frustrating than a breadboard full of logic chips.

The BORA is based around a CPLD – a cousin of the FPGA-powered devices we see from time to time – that allows any student of digital logic to program the device and fill macrocells with NANDs, NORs, and ANDs.

The Xilinx device used in the BORA has about 1600 gates that can be programmed; more than enough to complete all the projects in the online lectures [Colin] has put together. You can check out the documentation for the BORA over on the official site, and the demo video after the break.

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