iCE40

25 Articles

ICEBreaker, The Open Source Development Board For FPGAs

December 13, 2018 by 40 Comments

The Hackaday Superconference is over, which is a shame, but one of the great things about our conference is the people who manage to trek out to Pasadena every year to show us all the cool stuff they’re working on. One of those people was [Piotr Esden-Tempski], founder of 1 Bit Squared, and he brought some goodies that would soon be launched on a few crowdfunding platforms. The coolest of these was the iCEBreaker, an FPGA development kit that makes it easy to learn FPGAs with an Open Source toolchain.

The hardware for the iCEBreaker includes the iCE40UP5K fpga with 5280 logic cells,, 120 kbit of dual-port RAM, 1 Mbit of single-port RAM, and a PLL, two SPIs and two I2Cs. Because the most interesting FPGA applications include sending bits out over pins really, really fast, there’s also 16 Megabytes of SPI Flash that allows you to stream video to a LED matrix. There are enough logic cells here to synthesize a CPU, too, and already the iCEBreaker can handle the PicoRV32, and some of the RISC-V cores. Extensibility is through PMOD connectors, and yes, there’s also an HDMI output for your vintage computing projects.

If you’re looking to get into FPGA development, there’s no better time. Joe Fitz‘s WTFpga workshop from the 2018 Hackaday Superconference has already been converted to this iCEBreaker board, and yes, the seven-segment display and DIP switches are available. Between this and the Open Source iCE toolchain, you’ve got a complete development system that’s ready to go, fun to play with, and extremely capable.

Programming A RISC-V Softcore With Ada

October 8, 2018 by 9 Comments

We were contacted by [morbo] to let us know about a project on the AdaCore blog that concerns programming a PicoRV32 RISC-V softcore with Ada. The softcore itself runs on a Lattice ICE40LP8K-based TinyFPGA-BX FPGA board, which we have covered in the past.

The blog post describes how to use the Community edition of the GNAT Ada compiler to set up the development environment, before implementing a simple example project that controls a strip of WS28212b RGB LED modules. There are two push buttons changing the animation and brightness of the lights.

The source can be found at the author’s Github repository, and contains both the Ada source and the Verilog source for the PicoRV32 softcore. To build the project one needs the GNAT compiler, as well as the open-source iCE40 development tools to compile the softcore.

There is a video demonstrating the finished example project, that we’ve placed below the break.

Continue reading “Programming A RISC-V Softcore With Ada” →

Icestorm Tools Roundup: Open Source FPGA Dev Guide

October 3, 2018 by 7 Comments

We like the ICE40 FPGA from Lattice for two reasons: there are cheap development boards like the Icestick available for it and there are open source tools. We’ve based several tutorials on the Icestorm toolchain and it works quite well. However, the open source tools don’t always expose everything that you see from commercial tools. You sometimes have to dig a little to find the right tool or option.

Sometimes that’s a good thing. I don’t need to learn yet another fancy IDE and we have plenty of good simulation tools, so why reinvent the wheel? However, if you are only using the basic workflow of Yosys, Arachne-pnr, icepack, and iceprog, you could be missing out on some of the most interesting features. Let’s take a deeper look.

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Three Part Deep Dive Explains Lattice ICE40 FPGA Details

September 27, 2018 by 15 Comments

It is no secret that we like the Lattice iCE40 FPGA. It has a cheap development board and an open source toolchain, so it is an easy way to get started developing low-cost, low-power FPGA designs. There are a few members of the family that have similar characteristics including the top-of-the-line UltraPlus. [Steve] from Lattice and [Michael Klopfer] from the University of California Irvine have a three-part video series that explain the architecture of the devices. Altogether, the videos are about an hour long and — of course — they use the official tools, not IceStorm. But it is still a great time investment if you have an iCE40 board and you want to understand what the chip has under the hood.

The first part is fairly short and talks a lot about applications. There’s also a nod to the hobbyist use of FPGAs. Keep in mind that the iCE40 FPGAs come in different sizes and variants, so don’t get excited when you see them mention a RISC-V — that isn’t going to fit in your iCEStick, that we know of. The iCEstick has a HX-1K onboard, which is the high-performance variant with 1,280 logic elements, as opposed to the low-power (LP) version.

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An Ultrasound Driver With Open Source FPGAs

May 25, 2018 by 10 Comments

Ultrasound imaging has been around for decades, but Open Source ultrasound has not. While there are a ton of projects out there attempting to create open ultrasound devices, most of this is concentrated on the image-processing side of things, and not the exceptionally difficult problem of pinging a sensor at millions of times a second, listening for the echo, and running that through a very high speed ADC.

For his entry into the Hackaday Prize, [kelu124] is doing just that. He’s building an ultrasound board that’s built around Open Hardware, a fancy Open Source FPGA, and a lot of very difficult signal processing. It also uses some Rick and Morty references, so you know this is going to be popular with the Internet peanut gallery.

The design of the ultrasound system is based around an iCE40 FPGA, the only FPGA with an Open Source toolchain. Along with this, there are a ton of ADCs, a DAC, pulsers, and a high voltage section to drive the off-the-shelf ultrasound head. If you’re wondering how this ultrasound board interfaces with the outside world, there’s a header for a Raspberry Pi on there, too, so this project has the requisite amount of blog cred.

Already, [kelu] has a working ultrasound device capable of sending pulses out of its head and receiving the echo. Right now it’s just a few pulses, but this is a significant step towards a real, working ultrasound machine built around a reasonably Open Source toolchain that doesn’t cost several arms and legs.

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FPGA Design From Top To Bottom

October 24, 2017 by 20 Comments

[Roland Lutz] gave a talk about FPGA design using the free tools for Lattice devices at the MetaRheinMainChaosDays conference this year. You can see the video below. It’s a great introduction to FPGAs that covers both the lowest-level detail and some higher level insight. If you’re getting started with these FPGAs, this video is a must-see.

[Roland] starts with the obligatory introductory material. He then jumps into an actual example before zooming back out to look at the internal details of the Lattice FPGA. For instance, this FPGA supports multiple bitstreams, so you can switch between different “programs” on the fly.

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Learn FPGA Programming From The 1940s

October 5, 2017 by 11 Comments

We often think that not enough people are building things with FPGAs. We also love the retrotechtacular posts on old computer hardware. So it was hard to pass up [karlwoodward’s] post about the Chip Hack EDSAC Challenge — part of the 2017 Wuthering Bytes festival.

You might recognize EDSAC as what was arguably the first operational computer if you define a computer as what we think of today as a computer. [Maurice Wilkes] and his team invented a lot of things we take for granted today including subroutines (Wheeler jumps named after a graduate student).

The point to the EDSAC challenge was to expose people to creating designs with FPGAs, particularly using the Verilog hardware description language (HDL). If you want to follow along or run your own Chip Hack, the materials are available on the Web. You can see an FPGA driving a tape punch to create souvenir tapes in the video, below.

Some of the exercises are pretty simple and that’s perfect if you are starting out. The challenge uses a board with a Lattice ice40 FPGA and the open source toolchain for Lattice we’ve covered before. In fact, we’ve even done our own tutorials on the same basic device (but not the same board). Our final project generated PWM, not paper tape.

For the record, EDSAC was awesome. The execution unit was serial and processed bits that marched in one at a time over a mercury delay line. There is quite a bit of documentation and even some simulators, so if you ever wanted to get your hands into an old computer, this one isn’t a bad one to try.

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