The human auditory system is a complex and wonderful thing. One of its most useful features is the ability to estimate the range and direction of sound sources – think of the way people instinctively turn when hearing a sudden loud noise. A team of students have leveraged this innate ability to produce a game of tag based around nothing but sound.
The game runs on two FPGAs, which handle the processing and communication required. The chaser is given a screen upon which they can see their own location and that of their prey. The target has no vision at all, and must rely on the sounds in their stereo headphones to detect the location of the chaser and evade them as long as possible.
The project documentation goes into great detail about the specifics of the implementation. The game relies on the use of the Head Related Transfer Function – a function related to how the ear picks up sounds relative to their position. This allows the FPGA to simulate the chaser’s footsteps, and feed the audio to the target who perceives the chaser’s position purely by sound.
It’s a great example of a gameplay mechanic that we’d love to see developed further. The concept of trying to find one’s way around by hearing alone is one which we think holds a lot of promise.
With plenty of processing power under the hood, FPGAs are a great choice for complex audio projects. A great project to try might be decoding MP3s.
[Bruce Land] is one of those rare individuals who has his own Hackaday tag. He and his students at Cornell have produced many projects over the years that have appeared on these pages, lately with FPGA-related projects. If you only know [Land] from projects, you are missing out. He posts lectures from many of his classes and recently added a series of new lectures about developing with a DE1 System on Chip (SoC) using an Altera Cyclone FPGA using Verilog. You can catch the ten lectures on YouTube.
The class material is different for 2017, so the content is fresh and relevant. The DE1-SOC has a dual ARM processor and boots Linux from an SD card. There are several labs and quite a bit of background material. The first lab involves driving a VGA monitor. Another is a hardware solver for ordinary differential equations.
Continue reading “An Education on SoC using Verilog”
The Internet is full of low-speed logic analyzer designs that use a CPU. There are also quite a few FPGA-based designs. Both have advantages and disadvantages. FPGAs are fast and can handle lots of data at once. But CPUs often have more memory and it is simpler to perform I/O back to, say, a host computer. [Mohammad] sidestepped the choice. He built a logic analyzer that resides partly on an FPGA and partly on an ARM processor.
In fact, his rationale was to replace built-in FPGA logic analyzers like Chipscope and SignalTap. These are made to coexist with your FPGA design, but [Mohammad] found they had limitations. They also eat up die space you might want for your own design, so by necessity, they probably don’t have much memory.
The system can capture and display 32-bit signals on a 640×480 VGA monitor in real-time. The system also has a USB mouse interface which is used to zoom and scroll the display. You can see a video of the thing in operation, below.
Continue reading “Logic Analyzer on Chips”
Last time I looked at a simple 16-bit RISC processor aimed at students. It needed a little help on documentation and had a missing file, but I managed to get it to simulate using a free online tool called EDA Playground. This time, I’ll take you through the code details and how to run the simulation.
You’ll want to refer to the previous post if you didn’t read it already. The diagrams and tables give a high-level overview that will help you understand the files discussed in this post.
If you wanted to actually program this on a real FPGA, you’d have a little work to do. The memory and register initialization is done in a way that works fine for simulation, but wouldn’t work on a real FPGA. Anyway, let’s get started!
Continue reading “Simulating the Learn-by-Fixing CPU”
The usual way of adding GPS capabilities to a project is grabbing an off-the-shelf GPS module, plugging it into a UART, and reading the stream of NMEA sentences coming out of a serial port. Depending on how much you spend on a GPS module, this is fine: the best modules out there start up quickly, and a lot of them recognize the logical AND in ITAR regulations.
For [Mike], grabbing an off-the-shelf module is out of the question. He’s building his own GPS receiver from the ground up using a bit of hardware and FPGA hacking. Already he’s getting good results, and he doesn’t have to futz around with those messy, ‘don’t build ballistic missiles’ laws.
The hardware for this build includes a Kiwi SDR ‘cape’ for the BeagleBone and a Digilent Nexus-2 FPGA board. The SDR board captures raw 1-bit samples taken at 16.268 MHz, and requires a full minute’s worth of data to be captured. That’s at least 120 Megabytes of data for the FPGA to sort through.
The software for this project first acquires the GPS signal by finding the approximate frequency and phase. The software then locks on to the carrier, figures out the phase, and receives the 50bps ‘NAV’ message that’s required to find a position solution for the antenna’s location. The first version of this software was exceptionally slow, taking over 6 hours to process 200 seconds of data. Now, [Mike] has improved the channel tracking code and made it 300 times faster. That’s real-time processing of GPS data, using commodity off-the-shelf hardware. All the software is available on the Gits, making this a project that can very easily be replicated by anyone. We would expect the US State Department or DOD to pay [Mike] a visit shortly.
Of course, this isn’t the first time someone has built a GPS receiver from scratch. A few years ago, less than 1-meter accuracy was possible with an FPGA and a homebrew RF board.
There are two radio modulation schemes everyone should know. Amplitude modulation changes the amplitude — or ‘volume’, if you will — of a carrier frequency and turns all radio into channels owned and operated by a church. Frequency modulation changes the pitch of a carrier frequency and is completely run by Clear Channel. Amateur radio operators are familiar with dozens of other modulation schemes, but there’s one hardly anyone touches. Phase modulation is weird and almost unheard of, but that doesn’t mean you can’t implement it on an FPGA. [nckm] is transmitting audio using phase modulation on an FPGA (Russian, here’s the Google Translatrix).
This hardware is just an Altera MAX10 board, with a single input used for serial data of the audio to be transmitted, and two outputs, each connected to a few bits of wire for a quarter-wave antenna. No, there’s no output filter or anything else except for a few bits of wire. It’s an experiment, chillax.
The Verilog for this project receives an audio signal as serial data in mono, 22050 BPS, 8-bit unsigned samples. These samples are fed into a dynamic PLL with phase shift in the FPGA. Shifting the phases also changes the frequency, so [nckm] can receive this audio signal with the FM transmitter on his phone.
Is this really phase modulation if it’s being received by an FM radio? Eh, maybe. PM and FM are closely related, but certainly distinguishable as modulation schemes in their own right. You can grab [nckm]’s code over on the gits, or check out the video demo below.
Continue reading “Phase Modulation With An FPGA”
Because I often work with students, I’m always on the look-out for a simple CPU, preferably in Verilog, in the Goldilocks zone. That is, not too easy and not too hard. I had high hopes for this 16-bit RISC processor presented by [fpga4student], but without some extra work, it probably isn’t usable for its intended purpose.
The CPU itself is pretty simple and fits on a fairly long web page. However, the details about it are a bit sparse. This isn’t always a bad thing. You can offer students too much help. Then again, you can also offer too little. However, what was worse is one of the modules needed to get it to work was missing! You might argue it was an exercise left to the reader, but it probably should have been pointed out that way.
At first, I was ready to delete the bookmark and move on. Then I decided that the process of fixing this design and doing a little analysis on it might actually be more instructive than just studying a fully working design. So I decided to share my fix with you and look inside the architecture a bit more. On top of that, I’ll show you how to get the thing to run in an online simulator so you can experiment with no software installation. Of course, if you are comfortable with a Verilog toolchain (like the ones from Xilinx or Altera, or even free ones like Icarus or CVer) you should have no problem making that work, either. This time I’ll focus on how the CPU works and next time I’ll show you how to simulate it with some free tools. Continue reading “Learn by Fixing: Another Verilog CPU”