Al Williams Tells All In The Logic Simulation Hack Chat

March 4, 2022 by Tom Nardi 1 Comment

The list of requirements for hosting one of our weekly Hack Chats is pretty short: you’ve got to be knowledgeable, passionate, and above all else, willing to put those two quantities on display for a group of like-minded strangers. Beyond that, we’re not too picky. From industry insider to weekend hobbyist, high school dropout to double doctorate, if you’ve got something interesting to talk about, we’re ready to listen.

But in casting a such a wide net, we occasionally forget that we’ve got a considerable collection of potential hosts within our own worldwide roster of contributors. Among this cast of characters, few can boast the same incredible body of knowledge as Al Williams, who was able to pencil in some time this week to host the Logic Simulation Hack Chat.

Or at least, that was the idea. In reality the Chat covered a wide range of topics, and was peppered with fascinating anecdotes pulled from Al’s decades of experience in the field. Though to be fair, we expected no less. He was building hardware before many of us were born, and can take credit for designs that have been at the bottom of the ocean as well as launched into orbit. He’s been writing about it just as long too, with articles of his appearing in iconic print magazines such as Dr. Dobb’s Journal.

Al has seen and done so much that he still surprises us with the occasional nugget, and we’ve been working with him for years. It was only a week or two back that he started a story with “Back when I used to manage a gas pipeline…” in the middle of a conversation about utility metering.

Of course, that’s not to say some technical discussion didn’t sneak in there from time to time. Sure Al’s recollection of how they used to literally crawl over the schematics for the 68000 back at Motorola might stick out as a particular high point, but he also explains his personal preference for vendor-specific software tools over their more generic open source counterparts. He also draws comparisons between hardware description languages (HDLs) like Verilog and parametric CAD tools such as OpenSCAD in the way that they help model complex relationships in ways that can’t be easily done by more traditional means.

At one point the conversation lingers on the design and production of application-specific integrated circuits (ASICs), and how they compare to field-programmable gate arrays (FPGAs). Traditionally ASICs have been out of reach for the hobbyist, but with the recent collaboration between Google and SkyWater Technology to create an open source process design kit (PDK), they’re now within the capabilities of a dedicated individual. Matt Venn spoke on the topic during Remoticon 2021, and it’s good to see more folks in the community openly discussing the possibilities of custom silicon designed by hackers.

From there, things start really getting wild. From dreaming of virtual reality circuit simulators that let you fly amongst your creations like in Tron, to salivating over high-end technologies such as reflective memory, this Chat really runs the gamut. But then, that’s sort of why we hold them in the first place. Whether you actively participate or are just along for the ride, the Hack Chat gives everyone in the community a chance to gather around a virtual water cooler with fascinating characters that you won’t find anywhere else.

The Hack Chat is a weekly online chat session hosted by leading experts from all corners of the hardware hacking universe. It’s a great way for hackers connect in a fun and informal way, but if you can’t make it live, these overview posts as well as the transcripts posted to Hackaday.io make sure you don’t miss out.

Homebrew 16 Bit Computer Reinvents All The Wheels

December 3, 2021 by Ryan Flowers 23 Comments

Building your own computer has many possible paths. One can fabricate their own Z80 or MOS 6502 computers and then run a period correct OS. Or a person could start from scratch as [James Stanley] did. [James] has invented a completely unique computer and CPU he calls SCAMP. SCAMP runs a custom OS called SCAMP/os which you can check out in the video below the break.

[James] describes the CPU and computer as purposefully primitive. Built out of discrete 74xx series logic chips, it runs at a fast-enough-for-homebrew 1 MHz. Plus, it has a lot of blinking lights that can’t help but remind us of the original Imsai 8080. But instead of a panel of switches for programming, the SCAMP/os boots to a shell, which is presented through a serial terminal. Programs are written in a bespoke language with its own compiler. The OS is described as a having a Unix-like feel with CP/M-like functionality. That’s quite a combination!

What we love most about the build, other than its clean looks and blinkenlights, is the amount of work that [James] has put into documenting the build both on his blog and on Github, where the source code and design is available. There’s also an open invitation for contributors to help advance the project. We’re sure he’ll get there, one bit at a time.

While [James] is using a Compact Flash card for storage currently we can’t help but wonder if a Cassette Tape storage system might be a worthwhile future upgrade.

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Using VHDL To Generate Discrete Logic PCB Designs

November 13, 2021 by Zoe Skyforest 36 Comments

VHDL and Verilog are hardware description languages, used to describe and define logic circuits. They’re typically used to design ASICs and to program FPGAs, essentially using software to define hardware. However, [Tim] has done something altogether quite creative, creating tools to take VHDL and Verilog and spit out PCB designs for discrete logic.

Yes, you read that correctly. The basic idea is to take VHDL source code, and then make a PCB layout that implements the desired logic using resistor-transistor logic. From there, the PCB design files can be shipped off to a manufacturer for pick-and-place assembly at a fraction of the cost of producing a bespoke ASIC.

The drawbacks are obvious; tons of individual discrete parts are required, the size penalty is hilariously bad, and power usage is almost certainly orders of magnitude higher than doing the same logic on an ASIC or even FPGA. Oh, and everything’s much slower, too.

However, as an academic exercise or simply for fun, it’s an awesome bit of work. The idea that one can define a complicated logic circuit and have a PCB implementing the logic whipped up by automated tools is amazing, and we absolutely want to see more of this type of thing.

We’ve seen similar work done with VHDL synthesis into 74-series logic design. If you’ve been developing your own fancy digital-logic-fu, be sure to drop us a line!

[Thanks to Yann Guidon for the tip!]

RISC-V In… Typescript?

October 14, 2021 by Al Williams 8 Comments

We are accustomed to seeing RISC-V implementations in Verilog or VHDL, but [Low Level JavaScript] has one in TypeScript. Before you dismiss it as a mere emulator, know that the project relies on gateware-ts, a conversion between TypeScript and Verilog. From there, you can actually put the CPU on an FPGA. You can see the launch video below and there is one development video as well as, presumably, more to come.

We aren’t sure if many FPGA designers will be willing to switch to TypeScript. But if you are comfortable with it, it might open up FPGA development without having to learn as much of a new language.

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Slice Your Next FPGA Design

June 28, 2021 by Al Williams 12 Comments

A recent trend has been to convert high-level constructs into FPGA code like Verilog or VHDL. Silice goes the other way: it converts very hardware-specific concepts to Verilog and aims to be a more expressive and easier to use language.

Why Silice? The project’s web page enumerates its design goals:

A clean, simple syntax that clearly exposes the flow of operations and where clock cycles are spent.
Precise rules regarding flow control (loops, calls) and their clock cycle consumption.
Familiar hardware constructs such as always blocks, instantiation, expression tracking (wires).
An optional flow-control oriented design style (automatic FSM generation), that naturally integrates within a design: while, break, subroutines.
The possibility to easily describe pipelines.
Automatically takes care of creating flip-flops for variables, with automatic pruning (e.g. const or bindings).
Generic interfaces and grouped IOs for easy reuse and modular designs.
Generic circuits that can be instantiated and reused easily.
Explicit clock domains and reset signals.
Familiar syntax with both C and Verilog inspired elements.
Inter-operates with Verilog, allowing to import and reuse existing modules.
Powerful LUA-based pre-processor.

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FIR Filters For Xilinx

May 18, 2021 by Al Williams 7 Comments

Digital filters are always an interesting topic, and they are especially attractive with FPGAs. [Pabolo] has been working with them in a series of blog posts. The latest covers an 8th order FIR filter in Verilog. He covers some math, which you can find in many places, but he also shows how an implementation maps to DSP slices in a device. Then to reduce the number of slices, he illustrates folding which trades delay time for slice usage.

Folding takes a multi-stage parallel multiplication and breaks it into fewer multiplications done over a longer period of time. This reuses slices to reduce the number required for high-order filters.

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I’m Sorry Dave, You Shouldn’t Write Verilog

September 4, 2020 by Al Williams 54 Comments

We were always envious of Star Trek, for its computers. No programming needed. Just tell the computer what you want and it does it. Of course, HAL-9000 had the same interface and that didn’t work out so well. Some researchers at NYU have taken a natural language machine learning system — GPT-2 — and taught it to generate Verilog code for use in FPGA systems. Ironically, they called it DAVE (Deriving Automatically Verilog from English). Sounds great, but we have to wonder if it is more than a parlor trick. You can try it yourself if you like.

For example, DAVE can take input like “Given inputs a and b, take the nor of these and return the result in c.” Fine. A more complex example from the paper isn’t quite so easy to puzzle out:

Write a 6-bit register ‘ar’ with input
defined as ‘gv’ modulo ‘lj’, enable ‘q’, synchronous
reset ‘r’ defined as ‘yxo’ greater than or equal to ‘m’,
and clock ‘p’. A vault door has three active-low secret
switch pressed sensors ‘et’, ‘lz’, ‘l’. Write combinatorial
logic for a active-high lock ‘s’ which opens when all of
the switches are pressed. Write a 6-bit register ‘w’ with
input ‘se’ and ‘md’, enable ‘mmx’, synchronous reset
‘nc’ defined as ‘tfs’ greater than ‘w’, and clock ‘xx’.

Continue reading “I’m Sorry Dave, You Shouldn’t Write Verilog” →