For Christmas, [Hamster]’s wife gave him a mini-oven. Later that day, he tore it apart and built this FPGA controlled reflow oven.
We’ve seen plenty of reflow oven builds in the past. Most of those projects use a microcontroller to do closed loop control, sensing the temperature and toggling the heating element to hit a set point. This build uses the Papilo One FPGA development board as a controller. It implements a state machine that meets the reflow profile of the solder paste, ensuring SMD components are soldered properly.
The oven uses a MAX31855 to read temperature from a thermocouple. This device provides amplification, cold junction compensation, and analog to digital conversion which spits out the temperature over SPI. To control the heater, a 40A solid state relay is used.
The VHDL code that drives this oven is linked in the writeup, and has some interesting bits for those looking to experiment with FPGAs. It includes an SPI interface, display driver, and the temperature state machine logic.
For [Eric]’s entry for our Fubarino Contest, he went down to very low-level hardware and created Pong on an FPGA.
[Eric] used a Basys 2 FPGA board to create this virtual, logic gate version of Pong. Output is via the VGA port, multiplayer and an AI player is implemented, and all the required mechanics for Pong – collision detection, button and switch input, and score keeping are also in this project.
The Fubarino contest requires an easter egg, of course, so when the score for the left player reaches 13 and the score for the right player reaches 37 (get it? 1337?), the previously square ball turns into an extremely pixeley version of the Hackaday logo. The Hackaday URL is also displayed, thanks to [Eric]’s FP(V)GA module for displaying text on his FPGA board.
The improved Pong ball and URL only appears when the scores are 13-37, making this an extremely well-hidden easter egg. Video of [Eric] demoing his Pong below.
This is an entry in the Fubarino Contest for a chance at one of the 20 Fubarino SD boards which Microchip has put up as prizes!
Continue reading “Fubarino Contest: FPGA Pong”
We’ve seen FPGA dev boards out the wazoo—even some following the current trend of putting an FPGA and an ARM processor on a single board. Take one good idea and mix it in with a few million Linux/ARM boards already piling up on workbenches the world over and you get LOGi: an FPGA designed to plug into the Raspberry Pi and BeagleBone.
Both the Raspberry Pi and BeagleBone versions of the LOGi feature a Spartan 6 FPGA with 9152 logic cells, 16 DSP Slices, 576KB of RAM, and 96 I/O Pins. There’s also 256 MB of SDRAM and a SATA connector. The Kickstarter has a few demos for this board, namely a machine vision, Bitcoin mining (though don’t expect this board to make return-on-investment with mining), and an autonomous vehicle control demo. The LOGi’s hardware is comparable to the Papilio Pro, so potential projects may include generating NTSC video, adding a VGA out, and a few retrocomputer emulations via OpenCores.
For what this Kickstarter asks for the Pi or ‘Bone version of the LOGi—$89 USD for either—you’ll get a surprisingly capable FPGA dev board that’s a bit cheaper than comparable offerings. Sure, you won’t save any money buying a Pi and a LOGi, but if you have a few Raspberries lying about, you could do much worse for a starter FPGA board.
Thanks [hamster] for sending this one in.
[Brad Robinson] was feeling a bit nostalgic for his Microbee, so he rebuilt it in an FPGA. Not once, but three times. For the uninitiated, the Applied Technology Microbee was a Z80 based computer 1980’s. Designed in Australia, the Microbee did not see much popularity outside its home continent. Even so, the introduction to home computers many Australians was on a Microbee. [Brad] actually wrote several programs for the Microbee, including some games sold by Applied Technology themselves.
Fast forward to 2012, [Brad] is learning FPGAs, and wants to build a Microbee in VHDL. The FPGAbee was born. The first iteration of the FPGAbee began with the CPU, which came from the T80 open source VHDL Z80 core. Around this core [Brad] added the video controller, keyboard, and sound. When he started adding disk functionality, [Brad] ran into some problems. He wanted to use a FAT formatted SD card for cassette and hard disk emulation.
The relative complexities of the FAT format meant he would have to use some custom software to make this work. [Brad] decided to run this software on a second Z80 core. Both cores would need access to memory, and this is where [Brad] learned what he calls “a hard lesson in cross domain clocks” on FPGAs. Multiple clock nets can cause major propagation delay issues. [Brad] was able to work through the problems, but it caused him to step back and re-evaluate the entire design. This was the start of FPGABee2.
Continue reading “Build an FPGA Microbee in Three (Not so) Easy Steps”
There are very few ‘recent’ FPGAs out there that can be easily soldered. Due to their important number of IOs, they usually come in Ball Grid Array (BGA) packages. The Xilinx Spartan 6 LX9, a TQFP144 FPGA (having pins with a 0.5mm pitch) is one of the few exceptions that can be used to make low end development boards. However, it doesn’t have a lot of logic and memory resources or an on-chip Memory Control Block implemented in the silicon. Therefore, [Michael] designed an SDRAM controller with a small footprint for it.
Writing an SDRAM controller from scratch isn’t for the fainthearted – first of all you really have to know how SDRAM works (RAS, CAS, precharges, refresh cycles), and because of the high speed and accurate timing required you also have to learn some of the finer points of FPGA off-chip interfacing. In addition, most publicly available open cores are very complex – for example just the RTL core of the sdr_ctrl controller on opencores.org adds up to over 2,700 lines of Verilog. Even if it is not an accurate comparison metric, [Michael]’s controller is only 500 lines long.
While we’re sure most Hackaday readers were raised by arcade games featuring sprites, pixels, and other shiny brightly colored squares, this was not always so. Many classic arcade games – Lunar Lander, Gravitar, and Asteroids in particular – used vector displays. Instead of drawing individual pixels, these games functioned more like an oscilloscope, drawing lines. When [Todd] and [Andrew] got their hands on a monitor from an old Asteroids cabinet, they knew what they had to do: build their own vector arcade game.
The guys made their own DAC and Amplifier board that plugs right in to a Nexys2 FPGA dev board. This was after they tested out some 3D drawing code with a gnarly handmade R2R DAC they used to draw and rotate a cube on an oscilloscope screen.
Not only did the guys build a vector video card, they also connected the FPGA’s VGA out to a monochrome monitor for an in-game HUD. Awesome work that blows away anything available in the golden days of vector arcade games. It’s a beautiful piece of engineering that certainly deserves its own cabinet.
Video of the game available below.
Continue reading “Making vector arcade games with an FPGA”
[Chonggang Li] wrote in to share a link to the final project he and [Ran Hu] built for their embedded systems class. It’s called Piano Hero and uses an FPGA to implement a camera-based touch screen system.
All of the hardware used in the project is shown above. The monitor acts as the keyboard, using an image produced by the FPGA board to mark the locations of each virtual key. It uses a regular VGA monitor so they needed to find some way to monitor touch inputs. The solution uses a camera mounted above the screen at an obtuse angle. That is to say, the screen is tilted back just a bit which allows the images on it to be seen by the camera. The FPGA board processes the incoming image, registering a key press when your finger passes between the monitor and the camera. This technique limits the input to just a single row of keys.
This should be much simpler than using a CCD scanner sensor, but that one can track two-dimensions of touch input.
Continue reading “Camera-based touchscreen input via an FPGA”