The Zedboard uses Xilinx’s Zynq, which is a combination ARM CPU and FPGA. [Jeff Johnson] recently posted an excellent two-part tutorial covering using a Zedboard with multiple Ethernet ports. The lwIP (light-weight Internet Protocol) stack takes care of the software end.
Vivado is Xilinx’s software for configuring the Zynq (among other chips), and the tutorial shows you how to use it. The Ethernet PHY is an FPGA Mezzanine Card (FMC) with four ports that is commercially available. The project uses VHDL, but there is no VHDL coding involved, just the use of canned components.
The real issue when using an FPGA and a CPU is the interface between the processor and the FPGA circuitry. In this case, the ARM standard AXI bus does this task, and the Ethernet component properly interfaces to that bus. The IP application in the second part of the post is an echo server.
We’ve seen the Zynq used in flying machines and also in a music synthesizer. Although this project doesn’t use any Verilog or VHDL that you create, it is still a great example of configuring using Vivado and using common components in a design.
[Antti] has gained a bit of a reputation over on Hackaday.io – he has a tremendous number of FPGA projects on hackaday.io, and they’re all open source. If you’re looking for street cred with FPGAs, [Antti] has it. His Hands-on experience with FPGAs and CPLDs stretches back to the very first chips in the 70s. We’re so happy that he’s working to share this depth of knowledge, and that includes this talk he gave a few weeks ago at the Hackaday SuperConference. Take a look and then join us after the break for an overview of the FPGA terrain, then and now.
Continue reading “Antti Lukats: The Past, Present, And Future of Programmable Logic”
[Kodera2t] wanted to experiment with programmable logic. Instead of going with an FPGA board, he decided to build his own CPLD (complex programmable logic device) board, with a built-in programmer. The CPLD is a Xilinx 9536 which is inexpensive and, though obsolete, still readily available. The programmer for the board uses an FT232RL and the total cost is very low ([kodera2t] says it is in the price range of a Raspberry Pi Zero or about $4).
From a user’s point of view, a CPLD is just a small FPGA. Internally, there is a significant difference in how they implement your design. Although there are differences between different product families, CPLDs usually use a sea of logic gates arranged as an AND/OR chain. By feeding inputs and inverted inputs into the AND gates and then ORing the results, you can build interesting logic circuits. However, modern CPLDs use Verilog or VHDL, so you describe what you want just like with an FPGA and the software figures out how to use the underlying circuits to give you what you want.
Continue reading “Not Ready for FPGAs? Try a CPLD”
When you think of developing with FPGAs, you usually think of writing Verilog or VHDL. However, there’s been a relatively recent trend to use C to describe what an FPGA should do and have tools that convert that to an FPGA. However, at least in the case of Xilinx parts, this capability is only available in their newest tool (Vivado), and Vivado doesn’t target the older lower-cost FPGAs that most low-cost development boards use.
[Sleibso] who blogs for Xilinx, has an answer. It turns out you can use the Vivado C compilation tools to generate code for older FPGAs; it just involves a less convenient workflow. Vivado (even the free version) generates unique files that the rest of the tool uses to pick up compiled C code. However, it also generates RTL (Verilog or VHDL) as a by-product, and you can import that into the older ISE tool (which has a perfectly fine free version) and treat it as you would any other RTL files.
There’s an example of using the Vivado tool in the video below. [Sleibso] points out that the video is three years old, and the talk about licensing on the video is out of date. The free tools now including this capability. [Sleibso] talks about using a Spartan 6, but the same split workflow should work with most devices ISE supports.
Continue reading “Xilinx FPGAs in C for Free”
Tiny Linux computers are everywhere, and between BeagleBones, Raspberry and Banana Pis, and a hundred other boards out there, there are enough choices to go around. There is an extremely interesting ARM chip from Xilinx that hasn’t seen much uptake in the field of tiny credit-card sized computers: the Zynq. It’s an ARM Cortex-A9 coupled with an FPGA. It’s great for building peripherals that wouldn’t normally be included on a microcontroller. With Zynq, you just instantiate the custom bits in the FPGA, then interface them with a custom Linux driver. Thanks to CrowdSupply, there’s now a board out there that brings this intriguing chip to a proper development platform. It’s called the Snickerdoodle, and if you’ve ever wanted to see the capabilities of an FPGA tightly coupled to a fast processor, this is the board to watch.
The core of the Snickerdoodle is a Xilinx Zynq that features either a 667 MHz ARM Cortex A9 and a 430k gate FPGA (in the low-end configuration) or an 866 A9 and 1.3M gate FPGA. This gives the Snickerdoodle up to 179 I/O ports – far more than any other tiny Linux board out there.
Fully loaded, the Snickerdoodle comes with 2.4 and 5GHz WiFi, Bluetooth, 1GB of RAM, and an ARM Cortex A9 that should far surpass the BeagleBone and Raspberry Pi 2 in capabilities. This comes at a price, though: the top-shelf Snickerdoodle has a base price of about $150.
Still, the power of a fast ARM and a big FPGA is a big draw and we’re expecting a few more of these Zynq boards in the future. There are even a few projects using the Zynq on hackaday.io, including one that puts the Zynq in a Raspberry Pi-compatible footprint. That’s exceedingly cool, and we can’t wait to see what people will build with a small, fast ARM board coupled to an FPGA.
Back in 2012, [tmbinc] discovered a neat little undocumented feature in the Xilinx ISE: the ability to use TCP/IP instead of JTAG cables. [tmbinc] was working on an Open Hardware USB analyzer and discovered the nearly undocumented Xilinx Virtual Cable, a single ‘shift’ command that opens up a TCP connection and sends JTAG data out to another computer on the network. It’s extraordinarily useful, [tmbinc] wrote a daemon for this tool, and everything was right with the world.
Yesterday, [tmbinc] discovered the Xilinx Virtual Cable again, this time in one of Xilinx’s Github repos. The code was extraordinarily familiar, and looking closer at a few of the revisions, he saw it was very similar to code he had written three years ago.
The offending revision in the Xilinx repo is nearly identical to [tmbinc]’s Xilinx Virtual Cable Driver daemon. Variable names are the same, the variables are declared in the same order, and apart from whitespace, code conventions are the same. This is not to say someone at Xilinx stole code from [tmbinc], but if this were a computer science lab, there would be an academic disciplinary hearing. What’s worse, Xilinx plastered their copyright notice at the top of the code.
In an issue [tmbinc] raised, he said he was flattered, but clarified that his code was developed entirely from scratch. He believes the Xilinx code was derived from his own code written three years ago. Since [tmbinc]’s code was uploaded without a license, it defaulted to All Rights Reserved. This does not bode well for the Xilinx legal department.
In any event, you really, really have to wonder what Xilinx’s internal documentation looks like if a random person on the Internet can discover a barely-documented protocol, write a daemon, put it on the Internet, and have someone at Xilinx use that code.
Thanks to the anonymous tipster for sending this into the Hackaday tip jar.
The Red Pitaya is a credit-card sized board that runs Linux, has Ethernet, and a good bit of RAM. This sounds a lot like a Raspberry Pi and BeagleBone Black, but the similarities end there. The Red Pitaya also has two RF inputs, two RF outputs, and a load of digital IOs, all connected to an Xilinx SoC that includes an FPGA. [Pavel] realized the Pitaya had all the components of a software-defined radio, and built an implementation to prove it.
The input for the SDR taps directly into one of the high impedance inputs with a simple loop antenna made out of telephone cable. The actual software-defined part of this radio borrows heavily from an Xilinx application note, while everything is controlled by either SDR# or HDSDR.
[Pavel] included a pre-built SD card image with all his software, so cloning this project is simply a matter of copying an SD card and building an antenna. The full source is also available, interesting if you would like to muck about with FPGAs and SDRs.