Okay, now we’re beginning to feel a bit like [Alice]. This tutorial shows you how to simulate VHDL code. This code is intended to run on an FPGA and includes a software-only version of the AVR 8-bit microcontroller core. Essentially, you’ll simulate VHDL code that simulates AVR hardware. Wrap your mind around that!
The code is intended to run on a Papilio Field Programmable Gate Array development board. We saw an early version of this board running the AVR8 core about a year ago. However, you don’t need to have any hardware to follow along and recreate this simulation yourself. It might be a great way to get your feet wet with FPGA programming before making that first hardware buy. Five different screencasts take you through the process of getting the AVR8 code, using an altered Arduino IDE for it, setting up a free version of Xilinx ISE to run the simulation, then setting it free and interpreting the data that the simulator spits out the other end.
[Phil] over at Retroleum has cobbled together a clean, well put together laptop based entirely around a Zilog Z80 microprocessor and a pair of Spartan II FPGAs. These FPGAs allow him to reduce the number of devices on his board, and therefore cut his production cost as well as device size. He even managed to integrate a salvaged PSOne screen. The laptop comes complete with [Phil]’s own Homebrew OS as well as a great graphical vector based demo.
Sure he’s updated the project in recent years to shrink the board, speeding up the Z80, and increasing the peripheral speed and functionality, but we’re suckers here for a total package hack. Seriously though, check out the newest version of the device as well as the backlog that shows the project growing over time.
Thanks to [Steth] for the heads up.
[Chris Fenton] spent a year and a half constructing a 1/10th scale Cray-1 reproduction. The famous supercomputer was meticulously modelled in a field programmable gate array for a “nearly cycle-accurate” reproduction. [Chris’] hardware of choice for the project is a Xilinx Spartan-3E 1600 development board, using 75-80% of the available resources. The finished product runs at 33 MHz and is missing a few functions but it sounds like they don’t affect code execution. We like that he didn’t stop with the processor implementation, but also took the time to produce a case for the development board that looks just like the original.
Unlike the Atari 2600 FPGA project, we’re not quite sure what we’d use this for. But that doesn’t diminish the excellence of his work.
In our Dev Phone 1 excitement last week, we somehow overlooked phoneWreck’s teardown of the T-Mobile G1. The complex slider mechanism is certainly worth looking out. One of the major oddities they point out is the inclusion of two vibration motors. One is mounted next to the SIM on the mainboard. While the other is mounted in the frame next to the earpiece. We wonder what was gained/solved by using two. The phone also includes a digital compass module. We’d like a more detailed explanation of how the Xilinx CPLD is used. From this article in 2006, it seems HTC uses them to generate custom clock signals and switching off devices for power management.