ITER Dreams And The Practical Reality Of Making Nuclear Fusion Work On Earth

July 6, 2023 by Maya Posch 52 Comments

Doing something for the first time is tough. Yet to replicate the nuclear fusion process that powers the very stars, and do it right here on Earth in a controlled and sustained fashion is decidedly at the top of the list of ‘tough’ first times. What further complicates matters is when in order to even get to this ‘first’ you also add in a massive, international construction project and a heaping of geopolitics, all of which is a far cry from past nuclear fusion experiments.

With the International Thermonuclear Experimental Reactor (ITER) as the most visible part of nuclear fusion research, it is perhaps little wonder that the recent string of delays and budget increases is leading some to proclaim doom and gloom over the entire sector. This ironically in contrast with the recent news from the US’s NIF and its laser-based inertial confinement fusion, which is both state-funded and will never produce commercial power.

In light of this, it feels pertinent to ask the question of whether ITER is the proverbial white elephant, or even the mausoleum of international science that a recent article in Scientific American makes it out to be. Is fusion research truly doomed to peter out amidst the seemingly never-ending work on ITER?

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The I960: When Intel Almost Went RISC

July 4, 2023 by Maya Posch 27 Comments

The i960 KA/KB/MC/XA with the main functional blocks labeled. Click this image (or any other) for a larger version. Die image courtesy of Antoine Bercovici. Floorplan from The 80960 microprocessor architecture.

From the consumer space it often would appear as if Intel’s CPU making history is pretty much a straight line from the 4004 to the 8080, 8088 and straight into the era of Pentiums and Cores. Yet this could not be further from the truth, with Intel having churned through many alternate architectures. One of the more successful of these was the Intel i960, which is also the topic of a recent article by [Ken Shirriff].

Remarkably, the i960 as a solid RISC (Reduced Instruction Set Computer) architecture has its roots in Intel’s ill-fated extreme CISC architecture, the iAPX 432. As [Ken] describes in his comparison between the i960 and 432, both architectures are remarkably similar in terms of their instruction set, essentially taking what it could from the 432 project and putting it into a RISC-y shape. This meant that although the i960 could be mistaken as yet another RISC CPU, as was common in the 1980s, but integrated higher-level features as well, such as additional memory protection and inter-process communication. Continue reading “The I960: When Intel Almost Went RISC” →

Quantum Computing On A Commodore 64 In 200 Lines Of BASIC

July 4, 2023 by Maya Posch 17 Comments

The term ‘quantum computer’ gets usually tossed around in the context of hyper-advanced, state-of-the-art computing devices. But much as how a 19th century mechanical computer, a discrete computer created from individual transistors, and a human being are all computers, the important quantifier is how fast and accurate the system is at the task. This is demonstrated succinctly by [Davide ‘dakk’ Gessa] with 200 lines of BASIC code on a Commodore 64 (GitHub), implementing a range of quantum gates.

Much like a transistor in classical computing, the qubit forms the core of quantum computing, and we have known for a long time that a qubit can be simulated, even on something as mundane as an 8-bit MPU. Ergo [Davide]’s simulations of various quantum gates on a C64, ranging from Pauli-X, Pauli-Y, Pauli-Z, Hadamard, CNOT and SWAP, all using a two-qubit system running on a system that first saw the light of day in the early 1980s.

Naturally, the practical use of simulating a two-qubit system on a general-purpose MPU running at a blistering ~1 MHz is quite limited, but as a teaching tool it’s incredibly accessible and a fun way to introduce people to the world of quantum computing.

Four jumper wires with white heatshrink on them, labelled VCC, SCL, SDA and GND

Three Pitfalls In I2C Everyone Wishes Weren’t There

July 3, 2023 by Maya Posch 95 Comments

The best part of I2C is that it is a bus that is available just about anywhere, covering a vast ecosystem of devices that offer it as a hardware-defined interface, while being uncomplicated enough that it can also be implemented purely in software on plain GPIO pins. Despite this popularity, I2C is one of those famous informal standards that feature a couple of popular implementations, while leaving many of the details such as exact timing, bus capacitance and other tedious details to the poor sod doing the product development. Thus it is that we end up with articles such as a recent one on the tongue-twisting [pair of pared pears] blog, covering issues found while implementing an I2C slave.

As with any shared bus, whether multi-master or not, figuring out when the bus is clear is a fun topic, yet one which can cause endless headaches. One issue here comes from a feature that the SMBus version of I2C calls quick read/write. This allows for the rapid transfer of some data. Still, depending on the data returned by the slave, it may appear to the master that nothing is happening yet, since SDA is being held low by the slave until the stop condition, essentially locking the bus.

Where things get even more exciting comes generally in the form of what logic analyzers love to traumatically call a ‘spurious start/stop condition’. This refers to the behavior of SDA and SCL, with SDA going low before SCL indicating an error. This can occur due to a hold time that’s too low, causing other devices on the bus to miss the transition. Here SMBus defines a transition time of 300 ns, while I2C calls for 0 seconds, but it’s now suggested to delay calling a start/stop condition until a delay of 300 ns has passed. Essentially, it would seem that implementing a hold time is the way forward until evidence to the contrary appears.

The third pitfall pertains to the higher-speed modes of I2C, including Fast-Mode (FM) and Fast-Mode Plus (FM+). Backward compatibility with these higher speed versions is absent to spotty. Although FM+ (introduced by NXP in 2007) is supposed to be backward compatible with slower speeds, effectively the timing requirement differences between the FM+ and FM standards are too large to compensate for. At least in the current versions of the standards, but one of the joys of I2C is that there’s always another new set of revisions to look forward to.

The toroidal propeller's details in the CAD software. (Credit: rctestflight))

Testing Futuristic Propeller Designs With A 3D Printer And A Solar-Powered Boat

July 2, 2023 by Maya Posch 21 Comments

The toroidal boat propeller pair installed. (Credit: rctestflight)

As boring as propeller designs may seem to the average person, occasionally there’s a bit of a dust-up in the media about a ‘new’ design that promises at least a few percent improvement in performance, decreased noise profile, or any combination of such claims. Naturally, if you’re [Daniel Riley] of RCTestFlight, then you have to 3D print a few of them, and make a video covering a handful. Most famous of these is probably the toroidal propeller that made waves a while ago, mostly in the field of flying drones, but commercial toroidal boat props exist too.

Test results of the different boat propeller designs. (Credit: rctestflight)

Interestingly, the 2-blade FDM-printed propeller ended up performing the best, while the bi-blade design (with two sets of blades positioned one after the other) performed worse — but better than the toroidal design. Here the last two designs were professionally printed in nylon, rather than printed at home in a standard FDM printer with all of the surface sanding and treatment required. Even so, the surface treatment did not seem to noticeably affect the results in further testing.

Hints at the root cause of the problem came from the bubble tests. In a bubble test, air is blown in front of the spinning propeller to visualize the flow of the water. This revealed some stalling on the bi-blade and the toroidal design too, which would explain some of the performance loss. Going back between the CAD model and the design in the patent by Sharrow Marine didn’t provide any obvious hints.

Considering that this latter company claims a performance uplift over regular boat propellers, the next steps for [Daniel] would appear to involve some careful navigating between fluid dynamic modeling and claims made in glossy marketing material to figure out exactly how close someone at home with a 3D printer and some spare time can get to those claimed numbers.

(Heading image: The toroidal propeller’s details in the CAD software. (Credit: rctestflight) )

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Creating A Commodore 64 Cartridge On Single-Sided Stripboard

June 30, 2023 by Maya Posch 10 Comments

The DIY Commodore 64 cartridge. (Credit: Linus Åkesson)

When you want to write software for a system like the Commodore 64, the obvious and safe choice is to create an image that can be used with a tape or floppy drive emulator. Yet these come with the obvious disadvantage of loading time and manual steps, much like with the original hardware. Unfortunately, if you crave that instant-on experience that cartridges offer – courtesy of them being plugged directly into the system’s CPU bus – you better get an EE diploma to figure it all out. Or maybe not, as [Linus Åkesson] found out when he created a custom cartridge to boot his Commodordian project from.

For the core of the cartridge a bit of stripboard was sufficient to interface with the C64’s cartridge slot. Despite being single-sided, all the required signals were on one side of the slot. These include the EXROM line that informs the system that a cartridge is present, the ROML line that informs the cartridge when the system is trying to read from it, and of course the data bus. After this the interaction gets somewhat interesting, due to the use of the single-sided stripboard, as the address bus and other signals are on the non-connected side.

Working around this was the biggest challenge, but by creatively using the ROML and DotClk lines and by disabling the display output, the ATmega88 and 74HC541-based cartridge a working solution was created. There is still room for improvement here, naturally, but it would appear that if the goal is simply to autoload software on boot, this is definitely a workable solution. One could also splurge on double-sided stripboard, but that would strip away most of the fun of this solution.

Earth’s Final Frontier: Exploring The Alien Depths Of The Earth’s Oceans

June 28, 2023 by Maya Posch 29 Comments

Despite how hostile to life some parts of the Earth’s continents are, humanity has enthusiastically endeavored over the course of millennia to establish at least a toehold on each of them. Yet humanity has barely ventured beyond the surface of the oceans which cover around three-quarters of the planet, with human activity in these bodies of water dropping off quickly along with the fading of light from the surface.

Effectively, this means for all intents and purposes we have to this day not explored the vast majority of the Earth’s surface, due to over 70% of it being covered by water. As an ocean planet, much of Earth’s surface is covered by watery depths of multiple kilometers, with each 10 meters of water increasing the pressure by one atmosphere (1.013 bar), so that at a depth of one kilometer we’re talking about an intense 101 atmospheres.

Over the past decades, the 1985 discovery of Titanic’s wreck approximately 3.8 kilometer below the surface of the Atlantic, the two year long search for AF447’s black boxes, and the fruitless search for the wreckage of MH370 despite washed-up remnants have served as stark reminders of just how alien and how hostile the depths of the Earth’s oceans are. Yet with both tourism and mining efforts booming, will we one day conquer the full surface of Earth?

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