The Whiskey Pirates have once again dropped an excellent electronic badge for DEF CON 29. This is, of course, unofficial, but certainly makes the list of the hottest custom bling seen so far this year.
I’m not able to make it to the con in person, but the Pirates sent over one of these badges anyway for an early look. It’s gorgeous, and peering into the circuit board it would be easy to think that the chip shortage ain’t got nothin’ on this badge. But this was possible only because of some very creative parts sourcing, and a huge dose of inspired design work.
While ARM continues to make inroads into the personal computing market against traditional chip makers like Intel and AMD, it’s not a perfect architecture and does have some disadvantages. While it’s a great step on the road to software and hardware freedom, it’s not completely free as it requires a license to build. There is one completely open-source and free architecture though, known as RISC-V, and its design and philosophy allow anyone to build and experiment with it, like this build which implements a RISC-V processor in VHDL.
Since the processor is built in VHDL, a language which allows the design and simulation of integrated circuits, it is possible to download the code for the processor and then program it into virtually any FPGA. The processor itself, called NEORV32, is designed as a system-on-chip complete with GPIO capabilities and of course the full RISC-V processor implementation. The project’s creator, [Stephan], also struggled when first learning about RISC-V so he went to great lengths to make sure that this project is fully documented, easy to set up, and that it would work out-of-the-box.
Of course, since it’s completely open-source and requires no pesky licensing agreements like an ARM platform might, it is capable of being easily modified or augmented in any way that one might need. All of the code and documentation is available on the project’s GitHub page. This is the real benefit of fully open-source hardware (or software) which we can all get behind, even if there are still limited options available for RISC-V personal computers for the time being.
How does this compare to VexRISC or PicoSOC? We don’t know yet, but we’re always psyched to have choices.
Building your own CPU is arguably the best way to truly wrap your head around how all those ones and zeros get flung around inside of a computer, but as you can probably imagine even a relatively simple processor takes an incredible amount of time and patience to put together. Plus, more often than not you’re then left with a maze of wires and perfboards that takes up half your desk and doesn’t do a whole lot more than blink some LEDs.
But the Pineapple ONE, built by [Filip Szkandera] isn’t your average homebrew computer. Oh sure, it still took two years for him to design, debug, and assemble, his 32-bit RISC-V CPU and all its associated hardware; but the end result is a gorgeous looking machine that runs C programs and offers a basic interactive shell over VGA. In fact with its slick 3D printed enclosure, vertically stacked construction, and modular peripheral connections, it looks more like some kind of high-tech scientific instrument than a computer; homebrew or otherwise.
[Filip] says he was inspired to build this 500 kHz (yes, kilohertz) beauty using only discrete logic components by [Ben Eater]’s well known 8-bit breadboard computer and [Robert Baruch]’s LMARV-1 (Learn Me A RISC-V, version 1). He spent six months simulating the machine before he even started creating the schematics, let alone design the individual boards. He tried to keep all of his PCB’s under 100 x 100 mm to take advantage of discounts from the fabricator, which ultimately led to the decision to align the nine boards vertically and connect them together with pin headers.
In the video below you can see [Filip] start up the computer, call up a bit of system information, and even play a rudimentary game of snake before peeking and poking some of the machine’s 512 kB of RAM. It sounds like there’s still some work to be done and bugs to squash, but we’ve already seen enough to say this machine has more than earned entry into the pantheon of master-crafted homebrew computers.
If you’re a reader of Hackaday, then you’ve almost certainly encountered an Espressif part. The twin microcontroller families ESP8266 and ESP32 burst onto the scene and immediately became the budget-friendly microcontroller option for projects of all types. We’ve seen the line expand recently with the ESP32-C3 (packing a hacker-friendly RISC-V core) and ESP32-S3 with oodles of IO and fresh new CPU peripherals. Now we have a first peek at the ESP32-C6; a brand new RISC-V based design with the hottest Wi-Fi standard on the block; Wi-Fi 6.
There’s not much to go on here besides the standard Espressif block diagram and a press release, so we’ll tease out what detail we can. From the diagram it looks like the standard set of interfaces will be on offer; they even go so far as to say “ESP32-C6 is similar to ESP32-C3” so we’ll refer you to [Jenny’s] excellent coverage of that part. In terms of other radios the ESP32-C6 continues Espressif’s trend of supporting Bluetooth 5.0. Of note is that this part includes both the coded and 2 Mbps Bluetooth PHYs, allowing for either dramatically longer range or a doubling of speed. Again, this isn’t the first ESP32 to support these features but we always appreciate when a manufacturer goes above and beyond the minimum spec.
The headline feature is, of course, Wi-Fi 6 (AKA 802.11ax). Unfortunately this is still exclusively a 2.4GHz part, so if you’re looking for 5GHz support (or 6GHz in Wi-Fi 6E) this isn’t the part for you. And while Wi-Fi 6 brings a bevy of features from significantly higher speed to better support for mesh networks, that isn’t the focus here either. Espressif have brought a set of IoT-centric features; two radio improvements with OFDMA and MU-MIMO, and the protocol feature Target Wake Time.
OFDMA and MU-MIMO are both different ways of allowing multiple connected device to communicate with an access point simultaneously. OFDMA allows devices to slice up and share channels more efficiency; allowing the AP more flexibility in allocating its constrained wireless resources. With OFDMA the access point can elect to give an entire channel to a single device, or slice it up to multiplex between more than once device simultaneously. MU-MIMO works similarly, but with entire antennas. Single User MIMO (SU-MIMO) allows an AP and connected device to communicate using a more than one antenna each. In contrast Multi User MIMO (MU-MIMO) allows APs and devices to share antenna arrays between multiple devices simultaneously, grouped directionally.
Finally there’s Target Wake Time, the simplest of the bunch. It works very similarly to the Bluetooth Low Energy (4.X and 5.X) concept of a connection interval, allowing devices to negotiate when they’re next going to communicate. This allows devices more focused on power than throughput to negotiate long intervals between which they can shut down their wireless radios (or more of the processor) to extended battery life.
These wireless features are useful on their own, but there is another potential benefit. Some fancy new wireless modes are only available on a network if every connected device supports them. A Wi-Fi 6 network with 10 Wi-Fi 6 devices and one W-Fi 5 (802.11ac) one may not be able to use all the bells and whistles, degrading the entire network to the lowest common denominator. The recent multiplication of low cost IoT devices has meant a corresponding proliferation of bargain-basement wireless radios (often Espressif parts!). Including new Wi-Fi 6 exclusive features in what’s sure to be an accessible part is a good start to alleviating problems with our already strained home networks.
When will we start seeing the ESP32-C6 in the wild? We’re still waiting to hear but we’ll let you know as soon as we can get our hands on some development hardware to try out.
Thanks to friend of the Hackaday [Fred Temperton] for spotting this while it was fresh!
It’s an exciting time in the world of microprocessors, as the long-held promise of devices with open-source RISC-V cores is coming to fruition. Finally we might be about to see open-source from the silicon to the user interface, or so goes the optimistic promise. In fact the real story is considerably more complex than that, and it’s a topic [Andreas Speiss] explores in a video that looks at the issue with a wide lens.
He starts with the basics, looking at the various layers of a computer from the user level down to the instruction set architecture. It’s a watchable primer even for those familiar with the topic, and gives a full background to the emergence of RISC-V. He then takes Espressif’s ESP32-C3 as an example, and breaks down its open-source credentials. The ISA of the processor core is RISC-V with some extensions, but he makes the point that the core hardware itself can still be closed source even though it implements an open-source instruction set. His conclusion is that while a truly open-source RISC-V chip is entirely possible (as demonstrated with a cameo Superconference badge appearance), the importance of the RISC-V ISA is in its likely emergence as a heavyweight counterbalance to ARM’s dominance in the sector. Whether or not he is right can only be proved by time, but we can’t disagree that some competition is healthy.
We just got our hands on some engineering pre-samples of the ESP32-C3 chip and modules, and there’s a lot to like about this chip. The question is what should you compare this to; is it more an ESP32 or an ESP8266? The new “C3” variant has a single 160 MHz RISC-V core that out-performs the ESP8266, and at the same time includes most of the peripheral set of an ESP32. While RAM often ends up scarce on an ESP8266 with around 40 kB or so, the ESP32-C3 sports 400 kB of RAM, and manages to keep it all running while burning less power. Like the ESP32, it has Bluetooth LE 5.0 in addition to WiFi.
Espressif’s website says multiple times that it’s going to be “cost-effective”, which is secret code for cheap. Rumors are that there will be eight-pin ESP-O1 modules hitting the streets priced as low as $1. We usually require more pins, but if medium-sized ESP32-C3 modules are priced near the ESP8266-12-style modules, we can’t see any reason to buy the latter; for us it will literally be an ESP8266 killer.
On the other hand, it lacks the dual cores of the ESP32, and simply doesn’t have as many GPIO pins. If you’re a die-hard ESP32 abuser, you’ll doubtless find some features missing, like the ultra-low-power coprocessor or the DACs. But it does share a lot of the ESP32 standouts: the LEDC (PWM) peripheral and the unique parallel I2S come to mind. Moreover, it shares the ESP-IDF framework with the ESP32, so despite running on an entirely different CPU architecture, a lot of code will run without change on both chips just by tweaking the build environment with a one-liner.
If you were confused by the chip’s name, like we were, a week or so playing with the new chip will make it all clear. The ESP32-C3 is a lot more like a reduced version of the ESP32 than it is like an improvement over the ESP8266, even though it’s probably destined to play the latter role in our projects. If you count in the new ESP32-S3 that brings in USB, the ESP32 family is bigger than just one chip. Although it does seem odd to lump the RISC-V and Tensilica CPUs together, at the end of the day it’s the peripherals more than the CPUs that differentiate microcontrollers, and on that front the C3 is firmly in the ESP32 family.
Our takeaway: the ESP32-C3 is going to replace the ESP8266 in our projects, but it won’t replace the ESP32 which simply has more of everything when we need it. The shared codebase and peripheral architecture makes it easier to switch between the two when we don’t need the full-blown ESP32. In that spirit, we welcome the newcomer to the family.
But naturally, we’ve got a lot more to say about it. Specifically, we were interested in exactly what the RISC-V core brought to the table, and ran the module through power and speed comparisons with the ESP32 and ESP8266 — and it beats them both by a small margin in our benchmarks. We’ve also become a lot closer friends with the ESP-IDF SDK that all of the ESP32 family chips use, and love how far it has come in the last year or so. It’s not as newbie-friendly as ESP-Arduino, for sure, but it’s a ton more powerful, and we’re totally happy to leave the ESP8266 SDK behind us.
The Beagle V, a RISC-V-based single board computer from a collaboration between BeagleBoard and Seeed Studios aims to be “The First Affordable RISC-V Computer Designed to Run Linux”. RISC-V is the open-source processor architecture that everyone is interested in because it bypasses proprietary silicon of manufacturers such as Intel or AMD, allowing companies to roll their own silicon processors without licensing fees for the core.
BeagleBoard has long been one of the major players in the Single-Board Computer arena so far dominated by the Raspberry Pi. The board, slightly larger than the company’s previous offerings, features a StarFive dual-core 64-bit RISC-V processor running at a 1.0 GHz clock speed. The spec sheet on their GitHub repo indicates 4 and 8 GB RAM options, built-in WiFi and Bluetooth, and hardware video support for decoding, two camera connectors, one DSI connector for an external display, as well as a full-sized HDMI port. Gigabit Ethernet, four USB-3 ports, an audio jack, and USB-C as the power supply are packed onto the edges of the board. GPIO is routed to a 2×20 pin header.
Seeed Studio pegs the cost of the board at $149 for the 8 GB RAM version, although currently you must apply and be selected to purchase a board in this early stage. It’s unclear if the price will remain unchanged after this first run; the product page notes a coupon code is necessary and the Seeed Studios article indicates this is an introductory price. However, the same article also lists the 4 GB RAM variant at $119. The BeagleBoard page shows a timeline of April 2021 for a “pilot run for community”.
It’s exciting to see RISC-V continue to make inroads. This is a powerful board based around the core, and if successful it will help further prove the viability of open source processing cores in increasingly mainstream products.