FPGA

373 Articles

What’s The Difference Between Tang 9K And 20K (It Isn’t 11…)

June 6, 2024 by 18 Comments

[Grug Huhler] has been working with the Tang Nano 9K FPGA board. They are inexpensive, and he noticed there is a 20K version, so he picked one up. Of course, you’d expect the 20K board has a different FPGA with more gates than the 9K, but there are also a number of differences in the host board. [Grug] was kind enough to document the differences in the video below.

In addition to the differences, there’s a good demo of the boards hosting a system-on-chip design. The little DIP package is handy for breadboarding. All of the 20K pins are 3.3 V, according to the documentation. The 9K does have some 1.8 V pins. There are more external devices on the 20K board but that eats up more uncommitted pins. Depending on your design, that may or may not be a problem.

We keep meaning to pick some of these up to play with. The Verilog is easy enough, and the tools look adequate. If you need a refresher on Verilog, we have a boot camp for you that would probably port easily enough to the Tang system. We’ve been following [Grug’s] work on these chips lately, and you should, too.

Continue reading “What’s The Difference Between Tang 9K And 20K (It Isn’t 11…)” →

Use That One Port For High-Speed FPGA Data Export

June 1, 2024 by 10 Comments

There’s a good few options for exporting data out of FPGAs, like Ethernet, USB2, or USB3. Many FPGAs have a HDMI (or rather, sparkling DVI) port as well, and [Steve Markgraf] brings us the hsdaoh project — High-Speed Data Acquisition Over HDMI, using USB3 capture cards based on the Macrosilicon MS2130 chipset to get the data from the FPGA right to your PC.

Current FPGA-side implementation is designed for Sipeed Tang chips and the GOWIN toolchain, but it should be portable to an open-source toolchain in the future. Make sure you’re using a USB3 capture card with a MS2130 chipset, load the test code into your FPGA, run the userspace capture side, and you’re ready to add this interface to your FPGA project! It’s well worth it, too – during testing, [Steve] has got data transfer speeds up to 180 MB/s, without the USB3 complexity.

As a test, [Steve] shows us an RX-only SDR project using this interface, with respectable amounts of bandwidth. The presentation goes a fair bit into the low-level details of the protocol, from HDMI fundamentals, to manipulating the MS2130 registers in a way that disables all video conversion; do watch the recording, or at least skim the slides! Oh, and if you don’t own a capture card yet, you really should, as it makes for a wonderful Raspberry Pi hacking companion in times of need.

The 6809 Lives On In An FPGA

May 28, 2024 by 39 Comments

At one point, the Motorola 6809 seemed like a great CPU. At the time it was a modern 8-bit CPU and was capable of hosting position-independent code and re-entrant code. Sure, it was pricey back in 1981 (about four times the price of a Z80), but it did boast many features. However, the price probably prevented it from being in more computers. There were a handful, including the Radio Shack Color Computer, but for the most part, the cheaper Z80 and the even cheaper 6502 ruled the roost. Thanks to the [turbo9team], however, you can now host one of these CPUs — maybe even a better version — in an FPGA using Verilog.

The CPU may be old-fashioned on the outside, but inside, it is a pipeline architecture with a standard Wishbone bus to incorporate other cores to add peripherals. The GitHub page explains that while the 6809 is technically CISC, it’s so simple that it’s possible to translate to a RISC-like architecture internally. There are also a few enhanced instructions not present on the 6809.

In addition to the source code, you’ll find a thesis and some presentations about the CPU in the repository. While the 6809 might not be the most modern choice, it has the advantage of having plenty of development tools available and is easy enough to learn. Code for the 6800 should run on it, too.

Even using through-hole parts, you can make a 6809 computer fit in a tiny space.You can also break out a breadboard.

Peering Inside The Tang FPGA

May 6, 2024 by 14 Comments

[Grug] has been working with the Tang Nano 9K FPGA board. He wanted to use the Gowin Analysis Oscilloscope (GAO) to build an internal monitor into the device for probing internal points. The problem is that the documentation is a bit lacking, so he made a video showing how to make it work to help us all out.

The idea for this isn’t unique, although for some vendors, getting this capability requires you to buy a license or the free versions are limited. We were disappointed, as was [Greg], that he had to run Windows to get the software to work.

Continue reading “Peering Inside The Tang FPGA” →

Manta project logo - a manta ray, with cursive 'manta' written next to it

Manta: An Open On-FPGA Debug Interface

May 1, 2024 by 30 Comments

We always can use more tools for FPGA debugging, and the Manta project by [Fischer Moseley] delivers without a shadow of a doubt. Manta lets you add a debug and data transfer channel between your computer and your FPGA, that you can easily access with helpfully included Python libraries.

With just a short configuration file as input, it gives you cores you add into your FPGA design, tapping the signals of interest as an FPGA-embedded logic analyzer, interacting with registers, and even letting you quickly transfer tons of data if you so desire.

Manta is easy to install, is developer-friendly, has been designed in Amaranth, and is fully open source as you would expect. At the moment, Manta supports both UART and Ethernet interfaces for data transfer. As for embedding the Manta cores into your project, they can be exported to both Amaranth and Verilog. You should check out the documentation website — it contains everything you might want to know to get started quick.

The Manta project has started out as our hacker’s MIT thesis, and we’re happy that we can cover it for you all. FPGA-embedded logic analyzers are a fascinating and much-needed tool, and we’ve had our own [Al Williams] tell you about his on-FPGA logic analysis journey!

DIY 6 GHZ Pulse Compression Radar

April 6, 2024 by 10 Comments

Conceptually, radar is pretty simple: send out a radio wave and time how long it takes to get back via an echo. However, in practice, there are a number of trade-offs to consider. For example, producing a long pulse has more energy and range, but limits how close you can see and also the system’s ability to resolve objects that are close to each other. Pulse compression uses a long transmission that varies in frequency. Reflected waves can be reconstituted to act more like a short pulse since there is information about the exact timing of the reflected energy. [Henrik] didn’t want to make things too easy, so he decided to build a pulse compression radar that operates at 6 GHz.

In all fairness, [Henrik] is no neophyte when it comes to radar. He’s made several more traditional devices using a continuous wave architecture. However, this type of radar is only found in a few restricted applications due to its inherent limitations. The new system can operate in a continuous wave mode, but can also code pulses using arbitrary waveforms.

Some design choices were made to save money. For example, the transmitter and receiver have limited filtering. In addition, the receiver isn’t a superheterodyne but more of a direct conversion receiver. The signal processing is made much easier by using a Zynq FPGA with a dual-core ARM CPU onboard. These were expensive from normal sources but could be had from online Chinese vendors for about $17. The system could boot Linux, although that’s future work, according to [Henrik].

At 6 GHz, everything is harder. Routing the PCB for DDR3 RAM is also tricky, but you can read how it was done in the original post. To say we were impressed with the work would be an understatement. We bet you will be too.

Radar has come a long way since World War II and is in more places than you might guess. We hate to admit it, but we’d be more likely to buy a ready-made radar module if we needed it.

Linear Feedback Shift Registers For FPGAs

April 6, 2024 by 28 Comments

If you want to start an argument at a Hackaday meeting, you have only to ask something like “How much does this weigh?” or “What time is it?” But if you really want to start a street brawl, you can always say, “Are these numbers random?” Making random numbers that are actually random is actually a tough nut to crack. Most of what we do is, technically, pseudo-random (but we’ll say random number and assume you know what we mean). One way to generate seemingly random sequences is to use a linear feedback shift register or LFSR. You can use LFSRs in software, but they are also very useful in hardware design and [Adam Taylor] takes us through his use of them on FPGAs in a recent post. Continue reading “Linear Feedback Shift Registers For FPGAs” →