Pushing The FPGA Video Player Further

A fact universally known among the Hackaday community is that projects are never truly done. You can always spin another board release to fix a silkscreen mistake, get that extra little boost of performance, or finally spend the time to track down that weird transient bug. Or in [ultraembedded’s] case, take a custom FPGA player from 800 x 600 to 1280 x 720. The hardware used is a Digilent Arty A7 and PMOD boards for I2S2, VGA, and MicroSD. We previously covered this project back when it was first getting started.

Getting from 800 x 600 to 1280 x 720 — 31% more pixels — required implementing a higher performance JPEG decoder that can read in the MPJEG frames, pushing out a pixel every 2.1 clock cycles. The improvements also include a few convenience features such as an IR remote. The number of submodules inside the system is just incredible, with most of them being implemented or tweaked by [ultraembedded] himself.

For the FPGA Verilog, there’s the SD/MMC interface, the JPEG decoder, the audio controller, the DVI framebuffer, a peripheral core, and a custom RISC-V CPU. For the firmware loaded off the SD card, it uses a custom RTOS running an MP3 decoder, a FAT32 interface, an IR decoder, and a UI based on LVGL.

We think this project represents a wonderful culmination of all the different IP cores that [ultraembedded] has produced over the years. All the code for the FPGA media player is available on GitHub.

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A Scratch-built RISC-V CPU In An FPGA

“RISC architecture is going to change everything”, which is why [SHAOS] is building this cool RISC-V DIY retro-style computer.

The project took inspiration from another hacker’s work in building a RISC-V emulator; shared in the Hackaday FPGA chat. He took it a bit further and got it going on an UPDuino v2.0 board which features a iCE40 FPGA from Lattice.

The board passes all the tests for the RISC-V subset he’s aiming for and even run some Zephry RTOS examples. He’s done a really good job of documenting how he got the code to run as well as many of the experiments he’s run so far. All the project files for ICEcube2 software are posted. It’s not the only RISC-V CPU we’ve seen in an FPGA, but the code is actually very clear and worth a read if you’re into such things.

We think anyone interested in duplicating his work could do so somewhat easily and start playing around with this increasingly popular architecture. Or at least get some LED’s blinking in an arcane but meaningful way. Video after the break.

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A Completely Open Microcontroller

mriscv
An annotated mRISCV die image

We don’t know about you, but the idea of an Arduino-class microprocessor board which uses completely open silicon is a pretty attractive prospect to us. That’s exactly [onchipUIS]’s stated goal. They’re part of a research group at the Universidad Industrial de Santander and have designed and taped out a RISCV implementation with Cortex M0-like characteristics.

The RISCV project has developed an open ISA (instruction set architecture) for modern 32-bit CPUs. More than 40 research groups and companies have now jumped on the project and are putting implementations together.

[onchipUIS] is one such project. And their twitter timeline shows the rapid progress they’ve been making recently.

mriscv_bonding
Die directly bonded to an OSHPark PCB

After tapeout, they started experimenting with their new wirebonding machine. Wirebonding, particularly manual bonding, on a novel platform is a process fraught with problems. Not only have [onchipUIS] successfully bonded their chip, but they’ve done so using a chip on board process where the die is directly bonded to a PCB. They used OSHPark boards and described the process on Twitter.

The board they’ve built breaks out all the chip’s peripherals, and is a convenient test setup to help them validate the platform. Check it, and some high resolution die images, out below. They’re also sending us a die to image using our electron microscope down at hackerfarm, and we look forward to the results!

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