A Pi Pico soldered onto a custom breakout PCB, with an SD card connected to it using prototyping wires

RP2040 Runs Linux Through RISC-V Emulation

March 19, 2023 by 27 Comments

We’re used to running Linux on CPUs where it belongs, and the consensus is that RP2040 just isn’t up for the task – no memory controller, and nowhere near enough RAM, to boot. At least, that’s what you might believe until you see [tvlad1234]’s Linux-on-RP2040 project, reminding us there’s more than one way to boot Linux on a CPU like this! Just like with the “Linux on AVR” project in 2012 that emulated an ARM processor, the pico-rv32ima project emulates a RISC-V core – keeping up with the times.

Initially, the aforementioned “Linux on AVR through ARM” project was picked as a base – then, a newer development, [cnlohr]’s RISC-V emulator, presented itself and was too good to pass up on. Lack of RAM was fully negated by adding an SD card into the equation – coupled with a small caching layer, this is a crucial part for the project’s not-so-secret sauce. A fair amount of debugging and optimization later, [tvlad1234] got Linux to run, achieving boot times in 10-15 minutes’ ballpark – considering the emulation layer’s presence, this is no mean feat.

At this point, the boot process stalls as you enter a login shell. If Linux on RP2040 is within your area of interest, feel free to pick up the effort from here, as the project is fully open-source – you only need a Pi Pico board and a throwaway SD card! Now, if pairing a RP2040 with some classic software is your definition of an evening well-spent, you can’t go wrong with DOOM! However, if you’d rather play with something else *nix-like, we’ve seen someone port Fuzix onto the RP2040 before.

The Future Of RISC-V And The VisionFive 2 Single Board Computer

March 6, 2023 by 47 Comments

We’ve been following the open, royalty-free RISC-V ISA for a while. At first we read the specs, and then we saw RISC-V cores in microcontrollers, but now there’s a new board that offers enough processing power at a low enough price point to really be interesting in a single board computer. The VisionFive 2 ran a successful Kickstarter back in September 2022, and I’ve finally received a unit with 8 GB of ram. And it works! The JH7110 won’t outperform a modern desktop, or even a Raspberry Pi 4, but it’s good enough to run a desktop environment, browse the web, and test software.

And that’s sort of a big deal, because the RISC-V architecture is starting to show up in lots of places. The challenge has been getting real hardware that’s powerful enough to run Linux and compile software on, that doesn’t cost an arm and a leg. If ARM is an alternative architecture, then RISC-V is still an experimental one, and that is an issue when trying to use the VF2. That’s a theme we’ll repeat a few times, but the thing to remember here is that getting more devices in the wild is the first step to fixing things. Continue reading “The Future Of RISC-V And The VisionFive 2 Single Board Computer” →

Forth Cracks RISC-V

January 8, 2023 by 48 Comments

Over the decades there have been many programming languages, some of which have flowered briefly, and others that have stuck around despite newer, better, and faster competition. Few languages embody this last group more than FORTH, over five decades old and still cropping up wherever a simple, elegant, fast, and compact stack-based programming language fits the bill. [Alexander Williams] has now taken it somewhere new, with a FORTH in RISC-V assembly which runs on the GD32 series of microcontrollers that are RISC-V lookalikes of the popular STM32 ARM parts.

We have to admit to last having used FORTH on an 8-bit home computer in the 1980s, aside from a moment’s idle play on discovering that the Open Firmware on Apple computers is a FORTH interpreter. Thus we’re intrigued by this implementation, but not from a position of FORTH expertise. We’d expect such an efficient language to be extremely quick though, so it’s definitely something to keep an eye on for when a suitable dev board comes our way. If it interests you, take a look at the GitHub repository.

New Part Day: ESP32-P4 Espressif RISC-V Powerhouse

January 7, 2023 by 63 Comments

It seems every day there’s a new microcontroller announcement for which the manufacturer is keen to secure your eyeballs. Today it’s the turn of Espressif, whose new part is the ESP32-P4, which despite being another confusingly named ESP32, is a high-performance addition to their RISC-V line-up.

On board are dual-core 400 MHz and a single-core low power 40 MHz RISC-V processors, and an impressive array of hardware peripherals including display and camera interfaces and a hardware JPEG codec alongside the ones you’d expect from an ESP32 part. It’s got a whopping 768 KB of on-chip SRAM as well as 8 K of very fast cache RAM for intensive operations.

So after the blurb, what’s in it for us? It’s inevitable that the RISC-V parts will over time displace the Tensilica parts over time, so we’ll be seeing more on this processor in upcoming Hackaday projects. We expect in particular for this one to be seized upon by badge developers, who are intent on pushing extra functionality out of their parts.So we look forward to seeing the inevitable modules with this chip on board, and putting them through their paces.

Thanks [Renze] for the tip.

A Tiny RISC-V Emulator Runs Linux With No MMU. And Yes, It Runs DOOM!

December 7, 2022 by 28 Comments

It’s something of an article of faith, that to run Linux your computer must include a hardware memory management unit, or MMU. To an extent it’s true, in that for a Linux-based system to shine it must have that hardware, but in fact there has been support for MMU-less Linux for many years now. Prolific hacker [cnlohr] has created an emulated simple RISCV processor without an MMU, and not only does it run Linux, it also runs DOOM.

The videos below the break go into significant depth on writing and debugging an emulator not to mention the inner workings of DOOM, but fear not if it’s not your thing. Everything can be found in a GitHub repository, and there are straightforward instructions should you wish to try it yourself.

All this is entertaining stuff, but it becomes of much more interest when viewed as part of an ongoing chain of projects working on no-MMU Linux for low-end RISC-V microcontrollers. Imagine the prospect of running Linux on a CPU costing relative pennies, and you can see why that’s an interesting prospect. Even if it’s not the most unexpected way to run Linux without an MMU.

Continue reading “A Tiny RISC-V Emulator Runs Linux With No MMU. And Yes, It Runs DOOM!” →

Now The V In RISC-V Stands For VRoom

March 26, 2022 by 24 Comments

Hundreds of variations of open-source CPUs written in an HDL seem to float around the internet these days (and that’s a great thing). Many are RISC-V, an open-source instruction set (ISA), and are small toy processors useful for learning and small tasks. However, if you’re [Paul Campbell], you go for a high-end super-scalar, out-of-order, speculative, 8 IPC monster of a RISC-V CPU known as VRoom!.

That might seem a bit like word soup to the uninitiated in the processor design world (which is admittedly relatively small) but what makes this different from VexRISC is the scale and complexity. Rather than executing one instruction at a time sequentially, it executes multiple instructions, completing them concurrently in whatever order it can handle. The VexRISC chip is a good 32-bit modular design that can run Linux. It pulls a solid 1.57 DMIPS/MHz with everything turned on. The VRoom already clocks in at mighty 6.5 DMIPS/MHz, with more performance gains. It peaks at 8 instructions every clock cycle with a dual register file and a clever committing system to keep up.

VRoom is written in System Verilog to leverage Verilator (a handy linting and simulation framework), and while there is some C that generates different files, we’d wager it is pretty run-of-the-mill compared to a TypeScript based project. VRoom currently boots Linux thanks to an AWS-FPGA instance (a Xilinx VU9P Ultrascale), though it has to be trimmed to fit. [Paul] has big plans working his way up to a server-class chip with lots of cores and a huge cache.

It’s all on GitHub under a GPLv3 license; go check it out! [Paul] also has a talk with lots of great details. If you’re interested in getting into RISC-V but a server-class isn’t your speed, we heard Espressif is starting to use RISC-V cores in their ever-popular ESP series.

Clockwork DevTerm R-01 Takes RISC-V Out For A Spin

March 19, 2022 by 23 Comments

If you’re anything like us you’ve been keeping a close eye on the development of RISC-V: an open standard instruction set architecture (ISA) that’s been threatening to change the computing status quo for what seems like forever. From its humble beginnings as a teaching tool in Berkeley’s Parallel Computing Lab in 2010, it’s popped up in various development boards and gadgets from time to time. It even showed up in the 2019 Hackaday Supercon badge, albeit in FPGA form. But getting your hands on an actual RISC-V computer has been another story entirely. Until now, that is.

Clockwork has recently announced the availability of the DevTerm R-01, a variant of their existing portable computer that’s powered by a RISC-V module rather than the ARM chips featured in the earlier A04 and A06 models. Interestingly the newest member of the family is actually the cheapest at $239 USD, though it’s worth mentioning that not only does this new model only include 1 GB of RAM, but the product page makes it clear that the RISC-V version is intended for experienced penguin wranglers who aren’t afraid of the occasional bug.

Newbies are persona non grata for the R-01.

Beyond the RISC-V CPU and slimmed down main memory, this is the same DevTerm that our very own [Donald Papp] reviewed earlier this month. Thanks to the modular nature of the portable machine, this sort of component swapping is a breeze, though frankly we’re impressed that the Clockwork team is willing to go out on such a limb this early in the product’s life. In our first look at the device we figured at best they would release an updated CPU board to accommodate the Raspberry Pi 4 Compute Module, but supporting a whole new architecture is a considerably bolder move. One wonders that other plans they may have for the retro-futuristic machine. Perhaps a low-power x86 chip isn’t out of the question?