Die of an Altera EPM7032 EEPROM-based Complex Programmable Logic Device (CPLD). (Credit: ZeptoBars, Wikipedia)

Using EPROMS And EEPROMs As Programmable Logic With Lisp

October 28, 2023 by Maya Posch 9 Comments

That EPROMs, EEPROMs and kin can be used as programmable logic should probably not come as a major surprise, but [Jimmy] has created a Lisp-based project that makes using these chips as a logic array very straightforward. All it takes is importing the package into one’s Lisp project and defining the logic, before the truth function generates the binary file that can be written to the target chip.

Suggested is the one-time-programmable AT27C512R EPROM (64k x8), but any 8-bit parallel interface (E)EPROM should work, with non-OTP chips being nice unless the chip has to go into a production device. A possible future improvement is the addition of 16-bit (E)EPROM support.

The use of EEPROMs is common with PLA-replacements, as with, for example, the Commodore 64, where the official PLA IC tends to go bad over time. Due to the complexity of the logic in these PLA ICs, here CPLDs are used, which internally are still EEPROM-based, but feature many more programmable elements to allow for more complex logic. If all you need is a bit of glue logic and you are looking for something in between a stack of 74-logic ICs and a CPLD, an EEPROM may be just be the solution, regardless of whether you prefer to create the binary image with Lisp or C.

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FPGA Runs IBM 5151 MDA Display

September 13, 2023 by Lewin Day 11 Comments

When it comes to driving a display, you can do all kinds of fancy tricks with microcontrollers to get an image up. Really, though, FPGAs are the weapon of choice for playing with these kinds of signals. [Ted Fried] put one to great work driving an ancient IBM 5151 MDA display, and shared his results on Hackaday.io.

The build relies on a Digilent Arty Z7-20 SOC FPGA development board, which has a beefy 600 MHz ARM processor on board. It also packs 500 MB of DRAM—more than enough for storing pixel data for an ancient display.

To drive the old display, [Ted] whipped up a state machine on the FPGA. It’s tasked with fetching display data from RAM and creating the appropriate timings for the MDA display interface. The images are stored directly in an array in C code running on the ARM core. From there, they are copied into the FPGA’s RAM for trucking out to the display. The 720×350 images are stored as 1 bit per pixel, and are created by converting the original JPEGs into single-bit bitmaps in GIMP, before final conversion into a C code array via utility of [Ted’s] own design.

If you’ve ever wanted to display your images in resplendent amber or green, then this could be the project for you. It’s also just a great way to learn about using FPGAs and interfacing with alternative display technologies. If you’ve been whipping up your own retro display hacks, don’t hesitate to drop us a line.

The Another World Chip

July 14, 2023 by Jenny List 6 Comments

We cover many recreations of classic computer games on these pages, sometimes on original hardware, other times through ports to newer hardware, or even on emulators. But [Sylefeb]’s version of the Amiga classic Another World is in a class of its own. It doesn’t recreate an Amiga or run an emulator, instead it implements the game itself on a relatively modest Lattice UP5K FPGA.

This feat is possible because of the game’s architecture, it runs on a quite minimalist virtual machine that only needs blitter and rasterising hardware. This makes it a good candidate for the FPGA treatment. [Sylefeb] goes into a deep discussion of the hardware implemented in the FPGA, which makes a solid primer for how some of the 16-bit era games worked. In particular, we needed to read over the section about the rasterisation of polygons more than once. But it’s worth it.

The game can be run on a few dev boards featuring this FPGA, among which we’re particularly pleased to see the MCH 2023 conference badge. It requires a copy of the original to be owned for the game files, but we suspect if you’re this deep in you’d probably see that as a small price to pay.

FPGA Plays Tic-Tac-Toe

June 24, 2023 by Bryan Cockfield 18 Comments

As computers get more and more powerful and artificial intelligence algorithms improve, few games remain where the best humans can reliably beat their electronic counterparts. In chess this barrier was passed in 2005 with the last human win against a computer, and recently humans lost to computers at go. Simpler games like tic-tac-toe have been solved for all possible positions for a while now, so even a simple computer will always win or tie the game. But that doesn’t mean that there’s nothing left to learn about these games as [Hayden] demonstrates with this tic-tac-toe game built entirely on an FPGA.

[Hayden] is making this as part of a college course on digital design, so it really starts at first principles for working with FPGAs. It’s programmed in Verilog on a Basys 3 board, which also hosts the switches used as the game’s input and handles the VGA video output as well. The build uses state machines to keep track of the moves played on each of the squares, and another state machine to keep track of whether or not the current game has been won. If so, it highlights the winning moves in red, and stops taking further inputs until it is reset. Some more logic ties everything together along with a customized VGA driver to produce the entire gaming experience.

A game like tic-tac-toe is a great way to master the fundamentals of a system like this before moving on to more complex programs, especially on an FPGA platform that might handle a lot of the things we take for granted on more traditional computing systems, such as the video output. If you’re interested in taking more of a deep dive into the world of FPGAs, we published a primer about them a few years ago that will get you started.

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FPGA Breakout Board For DIP Package Shenanigans

June 21, 2023 by Lewin Day 22 Comments

FPGAs are supremely flexible and powerful devices. However, they usually come in QFP or BGA packages that are altogether difficult for hobbyists to play with. The DIP-FPGA breakout board aims to solve that problem by using a carrier PCB to put an advanced chip in a friendlier form factor.

The board itself fits a DIP-20 form factor when soldered up with regular-pitch pin headers. It features a MachXO2-1200HC FPGA from Lattice Semiconductor. That’s the same chip as used on similar the TinyFPGA A2. With 18 GPIO, a DIP-20 layout is just about enough pins to take care of business. It’s intended specifically for use on breadboards or via regular IC sockets. There’s also a six-pin programming port laid out on the board that you can use with pogo pins or header connectors as you desire.

If you want to do some fancy signal stuff in an easy-to-prototype form factor, this could be the setup for you. If you want to buy one ready-made, they’re available on Tindie for the curious. In the meantime, consider whether this beefy FPGA Arduino concept could also propel your next project to greater heights.

Creating Lithography-Free Photonic Reprogrammable Circuits

June 20, 2023 by Maya Posch 2 Comments

The field of photonics has seen significant advances during the past decades, to the point where it is now an integral part of high-speed, international communications. For general processing photonics is currently less common, but is the subject of significant research. Unlike most photonic circuits which are formed using patterns etched into semiconductor mask using lithography, purely light-based circuits are a tantalizing possibility. This is the focus of a recent paper (press release, ResearchGate) in Nature Photonics by [Tianwei Wu] and colleagues at the University of Pennsylvania.

What is somewhat puzzling is that despite the lofty claims of this being ‘the first time’ that such an FPGA-like device has been created for photonics, this is far from the case, as evidenced by e.g. a 2017 paper by [Kaichen Dong] and colleagues (full article PDF) in Advanced Materials. Here the researchers used a slab of vanadium dioxide (VO₂) with a laser to heat sections to above 68 °C where the material transitions from an insulating to a metallic phase and remains that way until the temperature is lowered again. The μm-sized features that can be created in this manner allow for a wide range of photonic devices to be created.

A rewritable metacanvas. a) Schematic of laser writing different photonic operator patterns on a metacanvas. b) Temperature-dependentresistance of a VO2 film. c) Optical images from writing and erasing process on the metacanvas. . d) Diagram showing the mathematical matrix (F) is compiled onto a metacanvas in the form of a photonic operator for manipulation of light waveform (I ). e) Schematic of a metacanvas programmed as a beam steerer with a steering angle ϕ. (Credit: Dong et al., 2018) — A rewritable metacanvas. a) Schematic of laser writing different photonic operator patterns on a metacanvas. b) Temperature-dependent resistance of a VO2 film. c) Optical images from writing and erasing process on the metacanvas. . d) Diagram showing the mathematical matrix (F) is compiled onto a metacanvas in the form of a photonic operator for manipulation of light waveform. e) Schematic of a metacanvas programmed as a beam steerer with a steering angle ϕ. (Credit: Dong et al., 2018)

What does appear to be different with the photonic system presented by [Wu] et al. is that it uses a more traditional 2D approach, with a slab of InGaAsP on which the laser pattern is projected. Whether it is more versatile than other approaches remains to be seen, with the use of fully photonic processors in our computers still a long while off, never mind photonics-accelerated machine learning applications.

Bringing The PIO To The FPGA

May 22, 2023 by Matthew Carlson 10 Comments

We’ve seen some pretty incredible hacks using the Raspberry Pi 2040. However, one of the most exciting bits of hardware onboard is the Programmable I/O (PIO). Not content with it just being a part of RP2040-based projects, [Lawrie Griffiths] has been porting the PIO to Verilog so anyone can enjoy it.

This particular implementation is based only on the spec that Raspberry Pi provides. For assembling PIO code, [Lawrie] uses Adafruit’s pioasm assembler they use for their MicroPython framework. There’s a simulator to test different programs, and the project targets the Blackice MX and the Ulx3s. A few example programs are included in the repo, such as outputting a pleasant guitar note over I2S and driving a chain of WS2812s.

The project is still incomplete but slowly making progress. It’s an incredible feat of reverse engineering. While the simulator can be used to debug programs, step through instructions, and inspect waveforms, the ultimate value of bringing the PIO to other systems is that now we can re-use the code. Things like the can2040, an implementation of the CAN bus protocol using the PIO. Or even a PIO-based USB host.