A New 8-bit CPU For C

It is easy to port C compilers to architectures that look like old minicomputers or bigger CPUs. However, as the authors of the Small Device C Compiler (SDCC) found, pushing C into a typical 8-bit CPU is challenging. Lessons learned from SDCC inspired a new 8-bit architecture, F8. This isn’t just a theoretical architecture. You can find an example Verilog implementation in the SDDC project and on GitHub. The name choice may turn out to be unfortunate as there was an F8 CPU from Fairchild back in the 1970s that apparently few people remember.

In the video from FOSDEM 2025, [Phillip Krause] provides a nice overview of the how and why of F8. While it might seem odd to create a new 8-bit CPU when you can get bigger CPUs for pennies, you have to consider that 8-bit machines are more than enough for many jobs, and if you can squeeze one into an FPGA, it might be a good choice as opposed to having to get a bigger FPGA to hold your design and a 32-bit CPU.

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Homebrew CPU Gets A Beautiful Rotating Cube Demo

[James Sharman] designed and built his own 8-bit computer from scratch using TTL logic chips, including a VGA adapter, and you can watch it run a glorious rotating cube demo in the video below.

The rotating cube is the product of roughly 3,500 lines of custom assembly code and looks fantastic, running at 30 frames per second with shading effects from multiple light sources. Great results considering the computing power of his system is roughly on par with vintage 8-bit home computers, and the graphics capabilities are limited. [James]’s computer uses a tile map instead of a frame buffer, so getting 3D content rendered was a challenge.

The video is about 20 seconds of demo followed by a detailed technical discussion on how exactly one implements everything required for a 3D cube, from basic math to optimization. If a deep dive into that sort of thing is up your alley, give it a watch!

We’ve featured [James]’ fascinating work on his homebrew computer before. Here’s more detail on his custom VGA adapter, and his best shot at making it (kinda) run DOOM.

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Going Minimal: 64×4, The Fun In Functional Computing

If you’ve ever wondered what makes a computer tick, the Minimal 64×4 by [Slu4] is bound to grab your attention. It’s not a modern powerhouse, but a thoughtfully crafted throwback to the essence of computing. With just 61 logic ICs, VGA output, PS/2 input, and SSD storage, this DIY wonder packs four times the processing power of a Commodore 64.

What sets [Slu4]’s efforts apart is his refusal to follow the beaten track of CPU development. He imposes strict complexity limits on his designs, sticking to an ultra-minimalist Von Neumann architecture. His journey began with the ‘Minimal Ur-CPU’, a logic-chip-based computer that could crunch numbers but little else. Next came the ‘Minimal 64’, featuring VGA graphics and Space Invaders-level performance. The latest ‘Minimal 64×4’ takes it further, adding incredible speed while keeping the design so simple it’s almost ridiculous. It’s computing stripped to its rawest form—no fancy sound, no dazzling graphics, just raw resourcefulness.

For enthusiasts of retro-tech and DIY builds, this project is a treasure trove. From text editors to starfield simulations to Sokoban, [Slu4] proves you don’t need complexity to make magic. Continue reading “Going Minimal: 64×4, The Fun In Functional Computing”

Regular (Expression) Chess

[Nicholas Carlini] found some extra time on his hands over the holiday, so he decide to do something with “entirely no purpose.” The result: 84,688 regular expressions that can play chess using a 2-ply minmax strategy. No kidding. We think we can do some heavy-duty regular expressions, but this is a whole other level.

As you might expect, the code to play is extremely simple as it just runs the board through series of regular expressions that implement the game logic. Of course, that doesn’t count the thousands of strings containing the regular expressions.

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High Performance RISC-V

From the Institute of Computing Technology division of the Chinese Academy of Sciences and Peng Cheng Laboratory comes a high-performance and well-documented RISC-V core called XiangShan.

In the Git repository, you’ll find several branches including at least two stable branches: Yanqihu and Nanhu. The currently developed architecture, Kunminghu, is impressive, with a sophisticated instruction fetch unit, a reorder buffer, and a register renaming scheme.

The point of these types of circuits in a CPU is to allow multiple instructions to process at once. This also implies that instructions can be executed out of order. A cursory glance didn’t show any branch prediction logic, but that may be a limitation of the documentation. If there isn’t one, that would be an interesting thing to add in a fork if you are looking for a project.

On the computing side, the processor contains an integer block, a floating point unit, and a vector processor. Clearly, this isn’t a toy processor and has the capability to compete with serious modern CPUs.

There is a separate GitHub for documentation. It looks like they try to keep documentation in both Mandarin and English. You can also find some of the academic papers about the architecture there, too.

We love CPU design, and this is an interesting chance to contribute to an open CPU while there are still interesting things to do. If you need to start with something easier, plenty of small CPUs exist for educational purposes.

RISC CPU Lives In Excel

Last time we checked in on [Inkbox], he had made a 16-bit CPU in Excel. Impressive, but not really practical. Presumably, his latest project isn’t any more practical, but we suspect an 8-bit RISC CPU was easier to implement in Excel and probably runs faster, too. The new machine uses a stack architecture with a simplified instruction set of ten instructions. You can follow along with his Excel adventure in the video below.

If you think about it, you may decide that doing something like this in Excel is easy because you could just script it and use Excel as the user interface. That’s true, but that’s not how [Inkbox] does it. He won’t use scripts or IF statements in a cell. That makes things much harder.

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Close-up of a CPU

Register Renaming: The Art Of Parallel Processing

In the quest for faster computing, modern CPUs have turned to innovative techniques to optimize instruction execution. One such technique, register renaming, is a crucial component that helps us achieve the impressive multi-tasking abilities of modern processors. If you’re keen on hacking or tinkering with how CPUs manage tasks, this is one concept you’ll want to understand. Here’s a breakdown of how it works and you can watch the video, below.

In a nutshell, register renaming allows CPUs to bypass the restrictions imposed by a limited number of registers. Consider a scenario where two operations need to access the same register at once: without renaming, the CPU would be stuck, having to wait for one task to complete before starting another. Enter the renaming trick—registers are reassigned on the fly, so different tasks can use the same logical register but physically reside in different slots. This drastically reduces idle time and boosts parallel tasking. Of course, you also have to ensure that the register you are using has the correct contents at the time you are using it, but there are many ways to solve that problem. The basic technique dates back to some IBM System/360 computers and other high-performance mainframes.

Register renaming isn’t the only way to solve this problem. There’s a lot that goes into a superscalar CPU.

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