PCIe For Hackers: Our M.2 Card Is Done

July 25, 2023 by Arya Voronova 18 Comments

We’ve started designing a PCIe card last week, an adapter from M.2 E-key to E-key, that adds an extra link to the E-key slot it carries – useful for fully utilizing a few rare but fancy E-key cards. By now, the schematic is done, the component placement has been figured out, and we only need to route the differential pairs – should be simple, right? Buckle up.

Getting Diffpairs Done

PCIe needs TX pairs connected to RX on another end, like UART – and this is non-negotiable. Connectors will use host-side naming, and vice-versa. As the diagram demonstrates, we connect the socket’s TX to chip’s RX and vice-versa; if we ever get confused, the laptop schematic is there to help us make things clear. To sum up, we only need to flip the names on the link coming to the PCIe switch, since the PCIe switch acts as a device on the card; the two links from the switch go to the E-key socket, and for that socket’s purposes, the PCIe switch acts as a host.

While initially routing this board, I absolutely forgot about one more important thing for PCIe – series capacitors on every data pair, on the host TX side of the link. We need three capacitor pairs here – on TX of the PCIe switch uplink, and two pairs on TX side of the switch – again, naming is host-side. I only remembered this after having finished routing all the diffpairs, and, after a bit of deliberation, I decided that this is my chance to try 0201 capacitors. For that, I took the footprints from [Christoph]‘s wonderful project, called “Effect of moon phase on tombstoning” – with such a name, these footprints have got to be good.

We’ve talked about differential pair calculations before in one of the PCIe articles, and there was a demo video too! That said, let’s repeat the calculations on this one – I’ll show how to get from “PCB fab website information” to “proper width and clearance diffpairs”, with a few fun shortcuts. Our setup is, once again, having signals on outer layers, referenced to the ground layer right below them. I, sadly, don’t yet understand how to calculate differential impedance for signal layers sandwiched between two ground planes, which is to say – if there’s any commenters willing to share this knowledge, I’d appreciate your input tremendously! For now, I don’t see that there’d be a tangible benefit to such an arrangement, anyway.

Continue reading “PCIe For Hackers: Our M.2 Card Is Done” →

A bench setup with a spectrum analyzer and a PCB under test

Clever Test Rig Clarifies Capacitor Rules-of-Thumb

March 30, 2023 by Robin Kearey 5 Comments

If you’ve done any amount of electronic design work, you’ll be familiar with the need for decoupling capacitors. Sometimes a chip’s datasheet will tell you exactly what kind of caps to place where, but quite often you’ll have to rely on experience and rules of thumb. For example, you might have heard that you should put 100 µF across the power supply pins and 100 nF close to each chip. But how close is “close”? And can that bigger cap really sit anywhere? [James Wilson] has been doing research to get some firm answers to those questions, and wrote down his findings in a fascinating blog post.

A PCB used to measure the effect of capacitor placement — The test board has two-layer and four-layer sections. The inter-layer capacitance greatly affects the PDN’s performance in each case.

[James] designed a set of circuit boards that enabled him to place different types of capacitors at various distances along a set of PCB traces. By measuring the impedance of such a power distribution network (PDN) across frequency, he could then calculate its performance under different circumstances.

The ideal tool for those measurements would have been a vector network analyzer (VNA), but because [James] didn’t have such an instrument, he made a slightly simpler setup using a spectrum analyzer with a tracking generator. This can only measure the impedance’s magnitude, without any phase information, but that should be good enough for basic PDN characterization.

The results of [James]’s tests are pretty interesting, if not too surprising. For example, those 100 nF capacitors really ought to be placed within 10 mm of your chip if it’s operating at 100 MHz, but you can get away with even 10 cm if no signals go much above 1 MHz. A bulk 100 µF cap can be placed at 10 cm without much penalty in either case. Combining several capacitors of increasing size to get a low impedance across frequency is a good idea in principle, but you need to design the network carefully to avoid resonances between the various components. This is where a not-too-low equivalent series resistance (ESR) is actually a good thing, because it helps to dampen those resonances.

Overall, [James]’s blog post is a good primer on the topic, and gives a bit of much-needed context to those rules of thumb. If you want to dive deeper into the details of PDN design or the inductance of PCB traces, our own [Bil Herd] has made some excellent videos on those topics.

An ATX motherboard sits on a grey surface with the I/O in the foreground. Behind the I/O is a large image of Tux, the Linux penguin, taking up most of the PCB and winding its way around different components on the board. Tux is part of the PCB itself, with his feet, beak, and outline in gold, body in black silkscreen, and belly in green soldermask.

Designing Aesthetically-Pleasing PCBs

January 15, 2023 by Navarre Bartz 28 Comments

We’ve seen our share of custom PCBs here on Hackaday, but they aren’t always pretty. If you want to bring your PCB aesthetics up a notch, [Ian Dunn] has put together a guide for those wanting to get into PCB art.

There are plenty of tutorials about making a functional PCB, but finding information about PCB art can be more difficult. [Ian] walks us through the different materials available from PCB fabs and how the different layer features can affect the final aesthetic of a piece. For instance, while black and white solder mask are opaque, other colors are often translucent and affected by copper under the surface.

PCB design software can throw errors when adding decorative traces or components to a board that aren’t connected to any of the functional circuitry, so [Ian] discusses some of the tricks to avoid tripping up here. For that final artistic flair, component selection can make all the difference. The guide has recommendations on some of the most aesthetically pleasing types of components including how chips made in the USSR apparently have a little bit of extra panache.

If you want to see some more on PCB art, check out this work on full-color PCBs and learn the way of the PCB artist.

The Whole Thing In Python

January 2, 2023 by Elliot Williams 6 Comments

[hsgw] built a macropad in Python, and that’s not a strange language to choose to program the firmware in these days. But that’s just the tip of the iceberg. The whole process — from schematic capture, through routing and generating the PCB, and even extending to making the case — was done programmatically, in Python.

The macropad itself isn’t too shabby, sporting an OLED and some nice silkscreen graphics, but the whole point here is demonstrating the workflow. And that starts with defining the schematic using skidl, laying out the board with pcbflow, which uses a bunch of KiCAD footprints, and then doing the CAD design for a case in cadquery, which is kind of like OpenSCAD.

The result is that the whole physical project is essentially code-defined from beginning to end. We’re not sure how well all the different stages of the workflow play together, but we can imagine that this makes versioning a ton easier. Coding a PCB is probably overkill for something simple like this — you’d be faster to lay it out by hand for sure — but it doesn’t really scale. There’s definitely some level of complexity where you don’t want to be clicking an pointing, but rather typing. Think of this as the “hello world” to designing in code.

Some of the tools in the workflow were new to us, but if you’d like an in-depth look at cadquery, we’ve got you covered. [Tim Böscke]’s insane CPU made from 555 timers (yes, really) uses pcbflow. And if you’d like to dig back a bit into the origins of Python PCB design, this post introduces CuFlow, on which pcbflow was based.

PCB antenna rendered useless by overly enthusiastic copper fill.

The Many Ways You Can Easily Ruin Your PCB Antenna Design

November 1, 2022 by Maya Posch 28 Comments

PCB antenna impaired by copper fill and other attenuation sources.

We have all seen Printed Circuit Board (PCB) antennas: those squiggly bits of traces on PCBs connected often to a Bluetooth, WiFi or other wireless communication chip. On modules like for the ESP8266 and ESP32 platforms the PCB antennas are often integrated onto the module’s PCB, yet even with such a ready-made module it’s possible to completely destroy the effectiveness of this antenna. These and other design issues are discussed in this article by [MisterHW].

It covers a range of examples of poor design, from having ground fill underneath an antenna, to having metal near the antenna, to putting dielectric materials near or on top of the antenna. The effect of all of these issues is generally to attenuate the signal, sometimes to the point where the antenna is essentially useless.

Ultimately, the best PCB antenna design is one where there is no nearby copper fill, and there are no traces running near or on layers below the antenna. After all, any metal trace or component is an antenna, and any dielectric materials will dampen the signal. Fortunately, there is e.g. a free KiCad library with ready-to-use PCB antenna designs to help one get started with a custom design, as well as many other resources, covered in the article.

If you want to get really professional about checking the effectiveness of an antenna design, you’ll want to use a Network Vector Analyzer. These will also help you with tuning the capacitors used with the PCB antenna.

(Featured image: PCB antenna rendered useless by overly enthusiastic copper fill.)

Working With BGAs: Design And Layout

June 20, 2022 by Robin Kearey 27 Comments

The Ball Grid Array, or BGA package is no longer the exclusive preserve of large, complex chips on computer motherboards: today even simple microcontrollers are available with those little solder balls. Still, many hobbyists prefer to stay with QFP and QFN packages because they’re easier to solder. While that is a fair point, BGA packages can offer significant space savings, and are sometimes the only choice: with the ongoing chip shortage, some other package versions might simply be unavailable. Even soldering doesn’t have to be complicated: if you’re already comfortable with solder paste and reflow profiles, adding a BGA or two into the mix is pretty easy.

In this article we’ll show that working with BGA chips is not as difficult as it may seem. The focus will be on printed circuit board design: how to draw proper footprints, how to route lots of signals and what capabilities your PCB manufacturer should have. We’ll cover soldering and rework techniques in a future article, but first let’s take a look at why BGAs are used at all.

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PCB Thermal Design Hack Gets Hot And Heavy

April 8, 2022 by Tom Nardi 1 Comment

Thanks to the relatively recent rise of affordable board production services, many of the people reading Hackaday are just now learning the ropes of PCB design. For those still producing the FR4 equivalent of “Hello World”, it’s accomplishment enough that all the traces go where they’re supposed to. But eventually your designs will become more ambitious, and with this added complexity will naturally come new design considerations. For example, how do you keep a PCB from cooking itself in high current applications?

It’s this exact question that Mike Jouppi hoped to help answer when he hosted last week’s Hack Chat. It’s a topic he takes very seriously, enough that he actually started a company called Thermal Management LLC dedicated to helping engineers cope with PCB thermal design issues. He also chaired the development of IPC-2152, a standard for properly sizing board traces based on how much current they’ll need to carry. It isn’t the first standard that’s touched on the issue, but it’s certainly the most modern and comprehensive.

It’s common for many designers, who can be referencing data that in some cases dates back to the 1950s, to simply oversize their traces out of caution. Often this is based on concepts that Mike says his research has found to be inaccurate, such as the assumption that the inner traces of a PCB tend to run hotter than those on the outside. The new standard is designed to help designers avoid these potential pitfalls, though he notes that it’s still an imperfect analog for the real-world; additional data such as mounting configuration needs to be taken into consideration to get a better idea of a board’s thermal properties.

Even with such a complex topic, there’s some tips that are widely applicable enough to keep in mind. Mike says the thermal properties of the substrate are always going to be poor compared to copper, so using internal copper planes can help conduct heat through the board. When dealing with SMD parts that produce a lot of heat, large copper plated vias can be used to create a parallel thermal path.

Towards the end of the Chat, Thomas Shaddack chimes in with an interesting idea: since the resistance of a trace will increase as it gets hotter, could this be used to determine the temperature of internal PCB traces that would otherwise be difficult to measure? Mike says the concept is sound, though if you wanted to get an accurate read, you’d need to know the nominal resistance of the trace to calibrate against. Certainly something to keep in mind for the future, especially if you don’t have a thermal camera that would let you peer into a PCB’s inner layers.

A rig used to test thermal properties of different trace configurations.

While the Hack Chats are often rather informal, we noticed some fairly pointed questions this time around. Clearly there were folks out there with very specific issues that needed some assistance. It can be difficult to address all the nuances of a complex problem in a public chat, so in a few cases we know Mike directly reached out to attendees so he could talk them through the issues one-on-one.

While we can’t always promise you’ll get that kind of personalized service, we think it’s a testament to the unique networking opportunities available to those who take part in the Hack Chat, and thank Mike for going that extra mile to make sure everyone’s questions were answered to the best of his ability.

The Hack Chat is a weekly online chat session hosted by leading experts from all corners of the hardware hacking universe. It’s a great way for hackers connect in a fun and informal way, but if you can’t make it live, these overview posts as well as the transcripts posted to Hackaday.io make sure you don’t miss out.