pipeline

12 Articles

Continuous Integration: What It Is And Why You Need It

January 6, 2020 by 35 Comments

If you write software, chances are you’ve come across Continuous Integration, or CI. You might never have heard of it – but you wonder what all the ticks, badges and mysterious status icons are on open-source repositories you find online. You might hear friends waxing lyrical about the merits of CI, or grumbling about how their pipeline has broken again.

Want to know what all the fuss is about? This article will explain the basic concepts of CI, but will focus on an example, since that’s the best way to understand it. Let’s dive in. Continue reading “Continuous Integration: What It Is And Why You Need It” →

Getting Good At FPGAs: Real World Pipelining

June 12, 2018 by 16 Comments

Parallelism is your friend when working with FPGAs. In fact, it’s often the biggest benefit of choosing an FPGA. The dragons hiding in programmable logic usually involve timing — chaining together numerous logic gates certainly affects clock timing. Earlier, I looked at how to split up logic to take better advantage of parallelism inside an FPGA. Now I’m going to walk through a practical example by modeling some functions. Using Verilog with some fake delays we can show how it all works. You should follow along with a Verilog simulator, I’m using EDAPlayground which runs in your browser. The code for this entire article is been pre-loaded into the simulator.

If you’re used to C syntax, chances are good you’ll be able to read simple Verilog. If you already use Verilog mostly for synthesis, you may not be familiar with using it to model delays. That’s important here because the delay through gates is what motivates us to break up a lot of gates into a pipeline to start with. You use delays in test benches, but in that context they mostly just cause the simulator to pause a bit before introducing more stimulus. So it makes sense to start with a bit of background on delays.

Continue reading “Getting Good At FPGAs: Real World Pipelining” →

Pipelining Digital Logic In FPGAs

June 5, 2018 by 11 Comments

When you first learn about digital logic, it probably seems like it is easy. You learn about AND and OR gates and figure that’s not very hard. However, going from a few basic gates to something like a CPU or another complex system is a whole different story. It is like going from “Hello World!” to writing an operating system. There’s a lot to understand before you can make that leap. In this set of articles, I want to talk about a way to organize more complex FPGA designs like CPUs using a technique called pipelining.

These days a complex digital logic system is likely to be on an FPGA. And part of the reason we can get fooled into thinking digital is simple is because of the modern FPGA tools. They hide a lot of complexity from you, which is great until they can’t do what you want and then you are stuck. A good example of that is where you are trying to hit a certain clock frequency. If you aren’t careful, you’ll get a complaint from the tool that you can’t meet timing constraints.

Continue reading “Pipelining Digital Logic In FPGAs” →

Racing The Beam With Super Hexagon

May 13, 2015 by 24 Comments

Early game consoles like the Atari 2600 had a very, very limited amount of RAM. There wasn’t even enough RAM for all the pixels on the screen; instead, pixels were generated by the CPU as they were being drawn. It’s playing with scanlines and colorbusts with code, something we’re now calling. ‘racing the beam’ for some reason.

[Sam] is in the middle of an EE degree right now, and for a digital design class he needed to write some Verilog. At the time he was addicted to the game Super Hexagon, and the game mechanics are simple enough for an FPGA. He built his own implementation, but not one with framebuffers. He’s using a pipelined approach where each pixel’s value is calculated just a few clock cycles before it’s displayed. It vastly reduces the memory requirements, on his Altera DE1 board compared to the framebuffer approach.

Video below.

Continue reading “Racing The Beam With Super Hexagon” →

Retrotechtacular: Pipeline To The Arctic

December 16, 2014 by 42 Comments

They said it couldn’t be done, and perhaps it shouldn’t have been attempted. Shouldas and couldas aside, the oil crisis of the 1970s paved the legislative way for an 800-mile pipeline across the Alaskan frontier, and so the project began. The 48-inch diameter pipe sections would be milled in Japan and shipped to Alaska. Sounds simple enough. But of course, it wasn’t, since the black gold was under Prudhoe Bay in Alaska’s North Slope, far away from her balmy southern climes.

The Trans-Alaska Pipeline System was constructed in three sections: from Valdez to Fairbanks, Fairbanks to a point in the Brooks Pass, and south from Prudhoe Bay to the mountain handoff. Getting pipe to the Valdez and Fairbanks is no big deal, but there is no rail, no highway, and no standard maritime passage to Prudhoe Bay. How on earth would they get 157 miles worth of 58-foot sections of pipe weighing over 8 tons each up to the bubblin’ crude?

Continue reading “Retrotechtacular: Pipeline To The Arctic” →