Open Source IDE For FPGAs As QtCreator Learns Verilog

December 29, 2018 by 10 Comments

Classic battles: PC vs Mac, Emacs vs Vi, Tastes Great vs Less Filling, and certainly one that we debate around the Hackaday watercooler: command line or IDE? There’s something to be said for using good old command line tools, and even if you like to configure your favorite editor to be nearly an IDE, at least it is one you are familiar with and presumably leverage over several different uses.

Most commercial FPGA tools come with a heavy-weight IDE. The open source tools for Lattice (IceStorm) typically is driven by the command line or a makefile. Until now. [Rochus-Keller] released VerilogCreator which is a plugin for QtCreator.

We were impressed because as IDEs go, QtCreator is both useful and lightweight, two things that don’t go together for many similar tools. [FPGAwars] has had an IDE based on Atom (apio-ide) although it hasn’t been updated in nearly a year. IceStudio sees more updates, of course, but it isn’t so much an IDE as a GUI-based code builder.

[Rochus-Keller] says there’s more to come. However, even at this early stage the IDE does syntax coloring, tooltips, inline messages, and can analyze source code allowing you to cross-reference symbols as you’d expect. There are configurations for Icarus to do simulations or you can use Verilator or Yosys — the synthesizer behind IceStorm. It appears it can also interact with Tcl-based workflows like those used by most FPGA vendor IDEs.

There’s quite a bit still on the to-do list, so we are excited to see where this is going. QtCreator isn’t hard to learn and it doesn’t’ feel as bloated as some of the big IDEs like Eclipse. If you want a quick introduction to QtCreator, we did that already. If you want to draw boxes instead of writing Verilog directly, try IceStudio.

How A Microcontroller Hiding In A USB Port Became An FPGA Hiding In The Same

December 25, 2018 by 21 Comments

When you think of microcontroller development, you probably picture either a breadboard with a chip or a USB-connected circuit board. But Tim Ansell pictured an ARM dev board that is almost completely hidden inside of a USB port. His talk at the 2018 Hackaday Superconference tells that story and then some. Check out the newly published video, along with more details of the talk, after the break.

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RISC-V CPU Gets A Peripheral

November 26, 2018 by 15 Comments

One of the ways people use FPGAs is to have part of the FPGA fabric hold a CPU. That makes sense because CPUs are good at some jobs that are hard to do with an FPGA, and vice versa. Now that the RISC-V architecture is available it makes sense that it can be used as an FPGA-based CPU. [Clifford Wolf] created PicoSOC — a RISC-V CPU made to work as a SOC or System on Chip with a Lattice 8K evaluation board. [Mattvenn] ported that over to a TinyFPGA board that also contains a Lattice FPGA and shows an example of interfacing it with a WS2812 intelligent LED peripheral. You can see a video about the project, below.

True to the open source nature of the RISC-V, the project uses the open source Icestorm toolchain which we’ve talked about many times before. [Matt] thoughtfully provided the firmware precompiled so you don’t have to install gcc for the RISC-V unless you want to write you own software. Which, of course, you will.

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X-Ray Vision For FPGAs: Using Verifla

November 9, 2018 by 3 Comments

Last time I talked about how I took the open source Verifla logic analyzer and modified it to have some extra features. As promised, this time I want to show it in action, so you can incorporate it into your own designs. The original code didn’t actually capture your data. Instead, it created a Verilog simulation that would produce identical outputs to your FPGA. If you were trying to do some black box simulation, that probably makes sense. I just wanted to view data, so I created a simple C program that generates a VCD file you can read with common tools like gtkwave. It is all on GitHub along with the original files, even though some of those are not updated to match the new code (notably, the PDF document and the examples).

If you have enough pins, of course, you can use an external logic analyzer. If you have enough free space on the FPGA, you could put something like SUMP or SUMP2 in your design which would be very flexible. However, since these analyzers are made to be configurable from the host computer, they probably have a lot of circuitry that will compete with yours for FPGA space. You configure Verifla at compile time which is not as convenient but lets it have a smaller footprint.

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Logic Analyzers For FPGAs: A Verilog Odyssey

October 12, 2018 by 10 Comments

Sometimes you start something simple and then it just leads to a chain reaction of things. I wanted to write a post about doing state machines in Verilog and target the Lattice iCEstick board that we often use for quick FPGA projects. That led to a small problem: how do you show what’s going on inside? In this series of posts, we’ll look at building a logic analyzer into an FPGA to help debug itself, instantiating memory, and — finally — state machines.

Logic analysis is a common tool in FPGA development. If you use Altera, they have Signal Tap available that lets you build a simple logic analyzer into the FPGA that talks back to your PC. Xilinx has ChipScope which is about the same. Sometimes those tools either cost money or are limited in some way in the free versions. I have my sights set on a tool that can be used with the Lattice architecture.

Sure, you can ship data out on I/O pins and then use a regular logic analyzer to pick up the data. But that isn’t very handy. So I thought about writing a generic logic analyzer component. But before I did I decided to check to see if someone else had already done it.

Spoiler alert: they did, but I wanted something a little different so I wound up extending the program significantly. What I wound up with is a reasonably portable Verilog logic analyzer that can produce traces like this one:

Keep in mind, this isn’t a simulation. This is real data pulled off the actual FPGA. Yes, that is gtkwave producing the plots, but the input data is a VCD file generated from samples taken inside the FPGA.

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Friday Hack Chat: FPGA Bootcamp

October 10, 2018 by No comments

For this week’s Hack Chat, we’re going to be talking all about FPGAs, with our own resident FPGA expert.

This summer, Hackaday.io launched FPGA bootcamps, simple, easy-to-follow tutorials that will get you up and running with Verilog. These were all done by Al Williams, Hackaday’s resident FPGA hacker. Al’s an electrical engineer, author of over thirty books, countless magazine articles, and thousands of blog posts. He’s been an amateur radio operator for 41 years, and his first computer used an 1802 chip.

Now Al is putting a little bit of his wisdom over on Hackaday.io. He’s written up a bunch of tutorials that will get you started in programmable digital logic. Everything from a refresher on the ins and outs of nands and nors. a short introduction to Verilog, moving into sequential logic, to putting that code on real FPGA hardware is already up, and this bootcamp isn’t done yet.

If you want to get started in FPGA design, Al’s the guy you want to talk to. During this Hack chat, you’ll be able to ask questions about FPGAs, and about what’s coming up in future bootcamps. We’ll also be talking about Al’s other projects that you might see on Hackaday in the future, like the embedded logic analyzer, his IceStorm workflow, and much more.

During this Hack Chat, we’re going to be talking about:

  • How to use the FPGA tutorials
  • What other FPGAs you can use the tutorials for and how
  • Other Hackaday Bootcamp topics — FPGA or otherwise — that you’d like to see.

You are, of course, encouraged to add your own questions to the discussion. You can do that by leaving a comment on the FPGA Bootcamp Hack Chat and we’ll put that in the queue for the Hack Chat discussion.

join-hack-chat

Our Hack Chats are live community events on the Hackaday.io Hack Chat group messaging. This week we’ll be sitting down on Friday, October 12th, at noon, Pacific time. If time zones got you down, we have a handy time zone converter.

Click that speech bubble to the right, and you’ll be taken directly to the Hack Chat group on Hackaday.io.

You don’t have to wait until Friday; join whenever you want and you can see what the community is talking about.

Programming A RISC-V Softcore With Ada

October 8, 2018 by 9 Comments

We were contacted by [morbo] to let us know about a project on the AdaCore blog that concerns programming a PicoRV32 RISC-V softcore with Ada. The softcore itself runs on a Lattice ICE40LP8K-based TinyFPGA-BX FPGA board, which we have covered in the past.

The blog post describes how to use the Community edition of the GNAT Ada compiler to set up the development environment, before implementing a simple example project that controls a strip of WS28212b RGB LED modules. There are two push buttons changing the animation and brightness of the lights.

The source can be found at the author’s Github repository, and contains both the Ada source and the Verilog source for the PicoRV32 softcore. To build the project one needs the GNAT compiler, as well as the open-source iCE40 development tools to compile the softcore.

There is a video demonstrating the finished example project, that we’ve placed below the break.

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