Logic Analyzer On Chips

May 17, 2017 by Al Williams 9 Comments

The Internet is full of low-speed logic analyzer designs that use a CPU. There are also quite a few FPGA-based designs. Both have advantages and disadvantages. FPGAs are fast and can handle lots of data at once. But CPUs often have more memory and it is simpler to perform I/O back to, say, a host computer. [Mohammad] sidestepped the choice. He built a logic analyzer that resides partly on an FPGA and partly on an ARM processor.

In fact, his rationale was to replace built-in FPGA logic analyzers like Chipscope and SignalTap. These are made to coexist with your FPGA design, but [Mohammad] found they had limitations. They also eat up die space you might want for your own design, so by necessity, they probably don’t have much memory.

The system can capture and display 32-bit signals on a 640×480 VGA monitor in real-time. The system also has a USB mouse interface which is used to zoom and scroll the display. You can see a video of the thing in operation, below.

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Cornell Students Have Your Back

January 8, 2017 by Bryan Cockfield 21 Comments

Back problems are some of the most common injuries among office workers and other jobs of a white-collar nature. These are injuries that develop over a long period of time and are often caused by poor posture or bad ergonomics. Some of the electrical engineering students at Cornell recognized this problem and used their senior design project to address this issue. [Rohit Jha], [Amanda Pustis], and [Erissa Irani] designed and built a posture correcting device that alerts the wearer whenever their spine isn’t in the ideal position.

The device fits into a tight-fitting shirt. The sensor itself is a flex sensor from Sparkfun which can detect deflections. This data is then read by a PIC32 microcontroller. Feedback for the wearer is done by a vibration motor and a TFT display with a push button. Of course, they didn’t just wire everything up and call it a day; there was a lot of biology research that went into this. The students worked to determine the most ideal posture for a typical person, the best place to put the sensor, and the best type of feedback to send out for a comfortable user experience.

We’re always excited to see the senior design projects from university students. They often push the boundaries of conventional thinking, and that’s exactly the skill that next generation of engineers will need. Be sure to check out the video of the project below, and if you want to see more of this semester’s other projects, we have you covered there too. Continue reading “Cornell Students Have Your Back” →

Gravity Simulations With An FPGA

January 2, 2017 by Lewin Day 25 Comments

Gravity can be a difficult thing to simulate effectively on a traditional CPU. The amount of calculation required increases exponentially with the number of particles in the simulation. This is an application perfect for parallel processing.

For their final project in ECE5760 at Cornell, [Mark Eiding] and [Brian Curless] decided to use an FPGA to rapidly process gravitational calculations. This allows them to simulate a thousand particles at up to 10 frames per second. With every particle having an attraction to every other, this works out to an astonishing 1 million inverse-square calculations per frame!

The team used an Altera DE2-115 development board to build the project. General operation is run by a Nios II processor, which handles the VGA display, loads initial conditions and controls memory. The FPGA is used as an accelerator for the gravity calculations, and lends the additional benefit of requiring less memory access operations as it runs all operations in parallel.

This project is a great example of how FPGAs can be used to create serious processing muscle for massively parallel tasks. Check out this great article on sorting with FPGAs that delves deeper into the subject. Video after the break.

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Sorting Resistors With 3D Printing And A PIC

December 30, 2016 by Al Williams 20 Comments

If you aren’t old enough to remember programming FORTRAN on punched cards, you might be surprised that while a standard card had 80 characters, FORTRAN programs only used 72 characters per card. The reason for this was simple: keypunches could automatically put a sequence number in the last 8 characters. Why do you care? If you drop your box of cards walking across the quad, you can use a machine to sort on those last 8 characters and put the deck back in the right order.

These days, that’s not a real problem. However, we have spilled one of those little parts boxes — you know the ones with the little trays. We aren’t likely to separate out the resistors again. Instead, we’ll just treasure hunt for the value we want when we need one.

[Brian Gross], [Nathan Lambert], and [Alex Parkhurst] are a bit more industrious. For their final project in [Bruce Land’s] class at Cornell, they built a 3D-printed resistor sorting machine. A PIC processor feeds a resistor from a hopper, measures it, and places it in the correct bin, based on its value. Who doesn’t want that? You can see a video demonstration, below.

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Mag Lev Without The Train (But With An FPGA)

June 26, 2016 by Al Williams 4 Comments

It always surprises us that magnetic levitation seems to have two main purposes: trains and toys. It is reasonably inexpensive to get floating Bluetooth speakers, globes, or just floating platforms for display. The idea is reasonably simple, especially if you only care about levitation in two dimensions. You let an electromagnet pull the levitating object (which is, of course, ferrous). A sensor detects when the object is at a certain height and shuts off the magnet. The object falls, which turns the magnet back on, repeating the process. If you do it right, the object will reach equilibrium and hover near the sensor.

Some students at Cornell University decided to implement the control loop to produce levitation using an Altera FPGA. An inductive sensor determined the position of an iron ball. The device uses a standard proportional integral derivative (PID) control loop. The control loop and PWM generation occur in the FPGA hardware. You can see a video of their result, below.

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Recreating Chiptunes In Verilog

June 19, 2016 by Brian Benchoff 9 Comments

The semester is wrapping up at Cornell, and that means it’s time for the final projects from [Bruce Land]’s lab. Every year we see some very cool projects, and this year is no exception. For their project, [Andre] and [Scott] implemented the audio processing unit (APU) of the Nintendo Entertainment System (NES). This is the classic chiptune sound that regaled a generation with 8-bit sounds that aren’t really eight bits, with the help of a 6502 CPU that isn’t really a 6502 CPU.

Unlike the contemporaneous MOS 6581 SID, which is basically an analog synthesizer on a chip, the APU in the NES is extraordinarily spartan. There are two pulse wave channels, a triangle wave channel, a random noise channel, and the very rarely used delta modulation channel (DMC) used to play very low quality audio samples. This is a re-implementation of the NES APU for a university lab; it is very understandable that [Andre] and [Scott] didn’t implement the rarely used DMC.

Everything about the circuitry of the NES is well documented, so [Andre] and [Scott] had a great wiki for their research. At the highest level, the APU runs on a 894kHz clock and controls three channels through dedicated registers. These outputs are fed through a mixer, which the guys scaled and combined into a 16-bit output played through a Wolfson WM8731 audio codec.

After implementing the NES APU, [Andre] and [Scott] added an SD card reader that can read the Nintendo Sound Format – the standard distribution format for NES chiptunes – and emulated a 6502 to control the registers. The result is a relatively simple device that plays NES chiptunes with amazing accuracy. The sound files on the project report sound like the real thing, but this is entirely emulated on modern hardware.

FPGA Powers Blazingly Fast LED Matrix Audio Visualizer

June 13, 2016 by Gerrit Coetzee 14 Comments

[Sam Miller], [Sahil Gupta], and [Mashrur Mohiuddin] worked together on a very fast LED matrix display for their final project in ECE 5760 at Cornell University.

They started, as any good engineering students, by finding a way to make their lives easier. [Sam] had built a 32×32 LED matrix for another class. So, they made three more and ended up with a larger and more impressive 64×64 LED display.

They claim their motivation was the love of music, but we have a suspicion that the true reason was the love all EEs share for unnaturally bright LEDs; just look at any appliance at night and try not be blinded.

The brains of the display is an Altera DE2-115 FPGA board. The code is all pure Verilog. The FFT and LED control are implemented in hardware on the FPGA; none of that Altera core stuff. To generate images and patterns they wrote a series of python scripts. But for us it’s the particle test shown in the video below that really turns our head. This system is capable of tracking and reacting to a lot of different elements on the fly why scanning the display at about 310 FPS. They have tested display scanning at twice that speed but some screen-wrap artifacts need to be worked out before that’s ready for prime time.

The team has promised to upload all the code to GitHub, but it will likely be a while before the success hangover blows over and they can approach the project again. You can view a video interview and samples of the visualizations in the videos after the break.

Thanks to their Professor, [Bruce Land], for submitting the tip! His students are always doing cool things. You can even watch some of his excellent courses online if you like: Here’s one on the AVR micro-controller.

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