[Aerotenna] recently announced the first successful flight of an unmanned air vehicle (UAV) powered by a Xilinx Zynq processor running ArduPilot. The Zynq is a dual ARM processor with an onboard FPGA that can offload the processor or provide custom I/O devices. They plan to release their code to their OcPoC (Octagonal Pilot on a Chip) project, an open source initiative that partners with Dronecode, an open source UAV platform.
Over on Hackaday.io, [Dave Vandenbout] has posted the CAT board, a Raspberry Pi daughterboard hat that features a Lattice FPGA, 32 MB of RAM, EEPROM, and a few Grove and PMOD connectors. The CAT takes advantage of the open source tool chain available for Lattice including the Python-based MyHDL (although, you could just use Verilog directly, if you prefer) and Icestorm. One interesting point: you can run the tool chain on the Raspberry Pi, resulting in a self-contained and largely portable FPGA development environment.
Tiny Linux computers are everywhere, and between BeagleBones, Raspberry and Banana Pis, and a hundred other boards out there, there are enough choices to go around. There is an extremely interesting ARM chip from Xilinx that hasn’t seen much uptake in the field of tiny credit-card sized computers: the Zynq. It’s an ARM Cortex-A9 coupled with an FPGA. It’s great for building peripherals that wouldn’t normally be included on a microcontroller. With Zynq, you just instantiate the custom bits in the FPGA, then interface them with a custom Linux driver. Thanks to CrowdSupply, there’s now a board out there that brings this intriguing chip to a proper development platform. It’s called the Snickerdoodle, and if you’ve ever wanted to see the capabilities of an FPGA tightly coupled to a fast processor, this is the board to watch.
The core of the Snickerdoodle is a Xilinx Zynq that features either a 667 MHz ARM Cortex A9 and a 430k gate FPGA (in the low-end configuration) or an 866 A9 and 1.3M gate FPGA. This gives the Snickerdoodle up to 179 I/O ports – far more than any other tiny Linux board out there.
Fully loaded, the Snickerdoodle comes with 2.4 and 5GHz WiFi, Bluetooth, 1GB of RAM, and an ARM Cortex A9 that should far surpass the BeagleBone and Raspberry Pi 2 in capabilities. This comes at a price, though: the top-shelf Snickerdoodle has a base price of about $150.
Still, the power of a fast ARM and a big FPGA is a big draw and we’re expecting a few more of these Zynq boards in the future. There are even a few projects using the Zynq on hackaday.io, including one that puts the Zynq in a Raspberry Pi-compatible footprint. That’s exceedingly cool, and we can’t wait to see what people will build with a small, fast ARM board coupled to an FPGA.
The BBC Microcomputer System (or BBC Micro) was an innovative machine back in the early 1980’s. One feature that impressed reviewers was a “tube” interface that allowed the machine to become an I/O processor for an additional CPU. When the onboard 6502 became too slow, it could become a slave to a Z-80 or even an ARM processor. The bus was actually useful for any high-speed device, but its purpose was to add new processors, a feature Byte magazine called “innovative.”
[Hoglet67] has released a very interesting set of FPGA designs that allows a small board sporting a Xilinx Spartan 3 to add a 6502, a Z80, a 6809, or a PDP/11 to a BBC Micro via the tube interface. There’s something satisfying about a classic computer acting as an I/O slave to a fairly modern FPGA that implements an even older PDP/11.
Imagine that you’re running a conference and you want to do a professional job recording the speakers and their decks. You’ll need to record one video stream from the presenter’s laptop, and it’d be nice to have another of the presenter taken with a camera. But you also need to have the presenter’s screen displayed on a projector or two for the live audience. And maybe you’d like all of this dumped down to your computer so that you can simultaneously archive the presentation and stream it out over the Internet.
That’s exactly the problem that the hdmi2usb project tries to solve on the software side for open-source software conventions. And to go with this software, [Tim Ansell] has built the Numato Opsis FPGA video board, to tie everything together. What’s great about the platform is that the hardware and the firmware are all open source too.
Because everything’s open and it’s got an FPGA on board doing the video processing, you’re basically free to do whatever you’d like with the content in transit, so it could serve as an FPGA video experimenter board. It also looks like they’re going to port code over so that the Opsis could replace the discontinued, but still open source, Milkimist One video effects platform.
One thing that’s really cute about the design is that it reports over USB as being a camera, so you can record the resulting video on any kind of computer without installing extra drivers. All in all, it’s an FPGA-video extravaganza with a bunch of open-source software support behind it. Very impressive, [Tim]!
You have an FPGA circuit and you want the user to interact with your circuit by pushing a button. Clearly, you need a button, right? Not so fast! [Clifford Wolf] recently found a mysterious effect that lets him detect when someone pushes on his iCEstick board.
The video below shows the mystery circuit (which is just the stock iCEstick board), which appears to react any time you flex the PC board. The Verilog implements a simple ring oscillator (basically an inverter with its output tied to its input).
In the previous installment, we talked about why flip flops are such an important part of digital design. We also looked at some latch circuits. This time, I want to look at some actual flip flops–that is circuit elements that hold their state based on some clock signal.
Just like last time, I want to look at sequential building blocks in three different ways: at the abstraction level, at the gate level, and then using Verilog and two online tools that you can also use to simulate the circuits. Remember the SR latch? It takes two inputs, one to set the Q output and the other to reset it. This unassuming building block is at the heart of many other logic circuits.
A common enhancement to the SR latch is to include an enable signal. This precludes the output from changing when the enable signal is not asserted. The implementation is simple. You only need to put an additional gate on each input so that the output of the gate can’t assert unless the other input (the enable) is asserted. The schematic appears on the right.
In the case of this simulation (or the Verilog equivalent), the SR inputs become active high because of the inversion in the input NAND gates. If the enable input is low, nothing will change. If it is high, then asserted inputs on the S or R inputs will cause the latch to set or reset. Don’t set both high at the same time when the enable is high (or, go ahead–it is a simulation, so you can’t burn anything up).(Note: If you can’t see the entire circuit or you see nothing in the circuit simulator, try selecting Edit | Centre Circuit from the main menu.)
