New Part Day: The RISC-V Chip With Built-In Neural Networks

October 8, 2018 by Brian Benchoff 87 Comments

After exploring a few random online shops one day, [David] (thanks for sending this in, by the way) ran across a very interesting chip. It’s a dual-core, RISC-V chip running at 400MHz. There’s 6 MB of SRAM on the CPU, and there’s 2MB for convolutional neural network acceleration. There is, apparently, WiFi on some versions. There are already SDKs available on GitHub, and a bare chip costs a dollar or two. Interested? Log in to Taobao, realize Taobao does pre-orders, and all this can be yours.

This is a preorder — because apparently you can do that as a seller on TaoBao, but the Sipeed M1 K210 is available as a ‘core’ board with 72 pins in a one-inch square package, a version with WiFi, or as a complete development board with an OV2640 camera, 2.4 inch LCD, microphone, and onboard USB. There are videos of this chip running a face detection routine. It found Obama.

A bit of googling tells us this chip comes from a company named Kendryte, and here the specs are repeated: this is a dual-core RISC-V with an FPU, a bunch of RAM, and can run TensorFlow. Documentation is available, although the datasheet will need to be translated, and as of this writing there’s a GitHub filled with SDKs and examples, with some of the repos updated in the last hour.

Over the years we’ve seen a few RISC-V chips given development boards, and you can buy them right now. The HiFive 1 is an exceptionally powerful microcontroller with processing power that puts it right up against the Teensy (which is built around a Freescale chip), but it’s also fairly expensive. We’re not sure the Arduino Cinque (also RISC-V) ever made it to production, but again, expensive. The idea that a RISC-V microcontroller could be available for just a few dollars is very interesting, it even comes with SDKs and utilities to make the chip useful.

Hackaday Links: July 15, 2018

July 15, 2018 by Brian Benchoff 29 Comments

Have you tried Altium CircuitMaker? Uh, you probably shouldn’t. [Dave] of EEVBlog fame informs us via a reliable source that CircuitMaker is intentionally crippled by adding a random sleep on high pad-count boards. The hilarious pseudocode suggested on the forum is if ((time.secs % 3) == 0) delayMicroseconds(padCount * ((rand() % 20) + 1));.Now, this is a rumor, however, I would assume [Dave] has a few back channels to Altium. Also, this assertation is supported by the documentation for CircuitStudio, which says, “While there are no ‘hard limits’ per se, the software has been engineered to make it impractical for use with large designs. To this end, the PCB Editor will start to exibit [sic] performance degradation when editing designs containing 5000 pads”. Chalk this up to another win for Fritzing; Fritzing will not slow down your computer on purpose.

Here’s an open challenge to everyone. As reported by [SexyCyborg], XYZPrinting (makers of the da Vinci printer) are patent trolling. This US patent is being used to take 3D printers off of the Amazon marketplace. Here’s the problem: no one can figure out what this patent is actually claiming. There’s something about multiple nozzles, and it might be about reducing nozzle travel, but I’m getting a ‘snap to bed’ vibe from this thing. Experts in 3D printing have no idea what this patent is claiming. The printer in question is the Ender 3, one of the first (actually the third…) China-based Open Source Hardware certified products, and it’s actually the best selling printer on Amazon at this time. I’m talking with Comgrow (the sellers of the Ender 3 on Amazon), and the entire situation is a mess. Look for an update soon.

Tired: Congress shall make no law… abridging the freedom of speech. Wired: But what if that speech is a gun? Wired‘s own Andy Greenberg advances the argument that computer code is not speech, contrary to many court rulings over the past 30 years (see Bernstein v. United States). Here’s the EFF’s amicus brief from the case. Read it. Understand it. Here’s a glowing Stephen Levy piece from 1994 on the export-controlled PGP for reference.

Like integrated circuits and microprocessors? Sure you do. Like drama? Oh boy have we got the thing for you. A week or so ago, ARM launched a website called RISC-V Basics (now unavailable, even from the Internet Archive, but you can try it here). It purports to settle the record on those new chips based on the capital-O Open RISC-V instruction set. In reality, it’s a lot of Fear, Uncertainty, and Doubt. This was an attempt by ARM Holdings to kneecap the upstart RISC-V architecture, but a lot of ARM engineers didn’t like it.

SiFive Releases Smaller, Lower Power RISC-V Cores

June 25, 2018 by Brian Benchoff 35 Comments

Today, SiFive has released two new cores designed for the lower end of computing. This adds to the company’s existing portfolio of microcontrollers and SoCs based on the Open RISC-V ISA. Over the last two years, SiFive has introduced a number of cores based on the RISC-V ISA, an Open Architecture ISA that gives anyone to design and develop a microcontroller or microprocessor platform. These two new cores fill out the low-power end of SiFive’s core portfolio.

The two new cores included in the announcement are the SiFive E20 and E21, both meant for low-power applications, and according to SiFive presentations, they’re along the lines of an ARM Cortex-M0+ and ARM Cortex-M4. This is a core — it’s not a chip yet — but since the introduction of SiFive’s first microcontrollers, many companies have jumped on the RISC-V bandwagon. Western Digital, for example, has committed to using the RISC-V architecture in SoCs and as controllers for hard drive, SSDs, and NASes.

The first chip from SiFive was the HiFive 1, which was based on the SiFive E31 CPU. We got our hands on the HiFive 1 early last year, and it is a beast. With the standard complement of benchmarks, in terms of raw power, it’s approximately twice as fast as the Teensy 3.6, based on the Kinetis K66, a 180 MHz ARM Cortex-M4F. The SiFive E31 is about 1.5 times as fast as the Teensy 3.6 on a pure calculations per clock basis. This is remarkable because the Teensy 3.6 is our go-to standard for when you want to toggle pins really really fast with a cheap, readily available microcontroller platform.

But sometimes you don’t need the fastest or best microcontroller. To that end, SiFive is looking toward a lower-power microcontroller based on the RISC-V core. The new offerings are built on the E2 Core IP series, with two standard cores. The E21 core provides mainstream performance for microcontrollers, and the E20 core is the most power-efficient core offered by SiFive. In effect, the E21 core is a replacement for the ARM Cortex-M3 and Cortex-M4, while the E20 is a replacement for the ARM Cortex-M0+.

Just a few months ago, SiFive released a gigantic, multicore, Linux-capable processor called the HiFive Unleashed. With support for DDR4 and Gigabit Ethernet, this chip would be more at home in a desktop than an Internet of Things thing. The most popular engine ever produced isn’t a seven-liter turbo diesel, it’s whatever goes into a Honda econobox; likewise, many more low-power microcontrollers like the Cortex-M0 and -M3 are sold than the newer, more powerful, and more expensive chips. Even though it’s not as exciting as a new workstation CPU, the world needs microcontrollers, and the more Open, the better.

Hackaday Links: April 8, 2018

April 8, 2018 by Brian Benchoff 7 Comments

SiFive raised $50 Million in funding. SiFive is a semiconductor working on two fronts: they want to democratize silicon prototyping, and they’re the people making the HiFive series of microcontrollers and SoCs. The HiFives are built on the RISC-V instruction set, a Big-O Open instruction set for everything from tiny microcontrollers to server CPUs. With RISC-V, you’re not tied to licensing from ARM or their ilk. Recently SiFive introduced an SoC capable of running Linux, and the HiFive 1 is a very fast, very capable microcontroller that’s making inroads with Nvidia and Western Digital. The new round of funding is great news for anyone who wants Open Source hardware, and the silicon prototyping aspect of it is exceptionally interesting. Great news for SiFive.

Guess what’s in just a few weekends? The Vintage Computer Festival Southeast. The VCFSE is Hotlanta’s own vintage computer festival, with a whole host of speakers, exhibits, and consignment to tickle those vintage dopamine receptors. On deck for the speakers is [Michael Tomczyk], one of the people responsible for the VIC-20, and [Scott Adams], no the other [Scott Adams], creator of adventure-style games for personal computers but not that adventure-style game. The exhibits will include Japanese retro computers, simulating an ENIAC and a mechanical keyboard meetup. If you’re around Georgia, this is an event worth attending.

Conference season is just around the corner, and you know what that means. It’s time to start ramping up for #badgelife. What is badgelife? It’s a hardware demoscene of electronic conference badges. This year, the badgelife scene has stumbled upon something everyone can get in on. Add-ons! They’re electronic hats (or shields, or capes) for all the badges. Physically, it’s a 2×2 pin header. Electronically, it’s power, ground and I2C. Want to prototype your own add-on? Good news, there’s a development board.

The Titius-Bode law states the semi-major axes of planets follow a geometric progression. The (simplified, incorrect) demonstration of this law states Mercury orbits at 0.25 AU, Venus at 0.5 AU, Earth at 1 AU, Mars at 2 AU, and continues to the outer planets. The Titius-Bode law is heavily discredited in the planetary science community, and any paper, talk, or manuscript is rejected by scientific editors out of hand. The Titius-Bode law is the planetary science equivalent of flat Earth conspiracy theories and Nazi moon bases; giving any consideration to the idea confirms you’re a moron. This week, some consulting firm posted something that is the Titius-Bode law on their blog. Why? So it could be submitted to Hacker News for that sweet SEO. This submission was upvoted to the top position, and is a wonderful springboard to argue an interesting point on media literacy. I posit the rise of news aggregators (facebook, twitter, digg, reddit, and HN), is the driving force behind ‘fake news’ as lay people become the gatekeepers. Prove me wrong.

The Department of Homeland Security has confirmed there are cell-site simulators (Stingrays, IMSI-catchers, or otherwise known as your own private cell phone base station) around Washington DC. It’s unknown who is operating these simulators, or even where they are. There are two things to read between the lines with this information: Duh, there are rogue Stingrays in DC. Holy crap duh. I bet there are also some around midtown Manhattan. You can buy the stuff to do this on eBay. Personally, I’ve found half a dozen Stingrays or other rogue cell stations this year (guess where?). Second, why is this a news item now? Is this a signal that the DHS will start clamping down on stuff you can buy on eBay? Hop to it, people; cellular hardware is a great way to make a liquid nitrogen generator.

A RISC-V That The Rest Of Us Can Understand

February 9, 2018 by Jenny List 32 Comments

There is great excitement in the world of microprocessors, surrounding the RISC-V architecture. This is an open source modular instruction set specification that has seen implementations on FPGAs, and is starting to emerge in dedicated silicon.

If you are not yet up to speed on what is probably going to be the most important microprocessor development of a generation, you should watch this video. As [Robert Baruch] sets out to demonstrate, the combination of RISC technology and a modular instruction set means that the simplest processor compliant with the RISC-V specification can be surprisingly accessible. And to demonstrate this he’s building one from LSI and MSI ~~TTL~~ CMOS chips, something we’d more usually expect to see in a recreation of a much older architecture.

The video below the break is the first of a forthcoming series, and in it he introduces the project and gives us an easily-understandable overview of RISC-V before explaining the mechanics of a register for his RISC-V implementation. This will be his first module, and he’s created a PCB for it. He runs through its design, his choice of indicator LEDs, and then his choice of PCB house. There is also a breakout board, with two of the PCI sockets he’ll be using for his backplane. Finally we see the board being tested, with LEDs lighting up in response to values being stored in a completed register.

[Robert] has appeared on these pages many times before, among the most recent with his TMS9900-based breadboard computer. This build moves away from his retro fare though, and should be well worth watching for future installments.

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SiFive Introduces RISC-V Linux-Capable Multicore Processor

February 3, 2018 by Brian Benchoff 39 Comments

Slowly but surely, RISC-V, the Open Source architecture for everything from microcontrollers to server CPUs is making inroads in the community. Now SiFive, the major company behind putting RISC-V chips into actual silicon, is releasing a chip that’s even more powerful. At FOSDEM this weekend, SiFive announced the release of a Linux-capable Single Board Computer built around the RISC-V ISA. It’s called the HiFive Unleashed, and it’s the first piece of silicon capable or running Linux on a RISC-V core.

The HiFive Unleashed is built around the Freedom U540 SOC, a quad-core processor built on a 28nm process. The chip itself boasts four U54 RV64GC cores with an additional E51 RV64IMAC management core. This chip has support for 64-bit DDR4 with ECC and a single Gigabit Ethernet port. Those specs are just the chip though, and you’ll really need a complete system for a single board computer. This is the HiFive Unleashed, a board sporting the Freedom U540, 8GB of DDR4 with ECC, 32MB of Quad SPI Flash, Gigabit Ethernet, and a microSD card slot for storage. If you don’t mind being slightly inaccurate while describing this to a technological youngling, you could say this is comparable to a Raspberry Pi but with a completely Open Source architecture.

News of this caliber can’t come without some disappointment though, and in this case it’s that the HiFive Unleashed will ship this summer and cost $999. Yes, compared to a Raspberry Pi or BeagleBone that is an extremely high price, but it has to be borne in mind that this is a custom chip and low-volume silicon on a 28nm process. Until a router or phone manufacturer picks up a RISC-V chip for some commodity equipment, this architecture will be expensive.

This announcement of a full Single Board Computer comes just months after the announcement of the SOC itself. Already, GCC support works, Linux stuff is going upstream, and the entire Open Source community seems reasonably enthusiastic about RISC-V. It’ll be great to see where this goes in the coming years, and when we can get Linux-capable RISC-V chips for less than a kilobuck.

SiFive Announces RISC-V SoC

October 4, 2017 by Brian Benchoff 33 Comments

At the Linley Processor Conference today, SiFive, the semiconductor company building chips around the Open RISC-V instruction set has announced the availability of a quadcore processor that runs Linux. We’ve seen RISC-V implementations before, and SiFive has already released silicon-based on the RISC-V ISA. These implementations are rather small, though, and this is the first implementation designed for more than simple embedded devices.

This announcement introduces the SiFive U54-MC Coreplex, a true System on Chip that includes four 64-bit CPUs running at 1.5 GHz. This SoC is built with TSMC’s 28 nm process, and fits on a die about 30 mm². Availability will be on a development board sometime in early 2018, and if our expectations match the reality of SiFive’s previous offerings, you’ll be able to buy this Open SoC as a BGA package some months after that.

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