RISC-V

86 Articles

An Entire RISC-V Operating System In 2000 Lines

May 18, 2023 by 34 Comments

While Microsoft and Apple don’t release the source code for their operating systems, a good estimate is that it takes around 50 million lines of code to run these software behemoths. The Linux kernel alone holds around 30 million lines, with systemd containing over one million lines on its own, which doesn’t include estimates for the desktop environment or other parts of a standard installation. But millions of lines of code, or even hundreds of thousands, aren’t necessary for building a fully functioning operating system. This one sets up a complete OS in exactly 2000 lines of code.

Called egos-2000, short for Earth and Grass Operating System, the diminutive operating system is written for RISC-V computers and while it does contain most of the tools we would recognize in an OS, it was built specifically for computer science students by PhD candidate Yunhao Zhang. The slimmed-down operating system makes it possible for students to easily read and understand every feature of an operating system without it becoming too overwhelming, and can be easily used and modified to experiment with. The name itself comes from its design principles, where parts of the operating system that interact with hardware directly are part of the “Earth” layer and parts that don’t depend on hardware being placed in the “Grass” layer, with applications taking up a third layer.

The OS is available on this GitHub page under an MIT license and works on real RISC-V hardware as well as within various emulators. Building a complete operating system in so few lines of code is an impressive feat, and making it comprehensive enough to teach students with goes well beyond that accomplishment as well. Often when concepts in computer science are reduced to their bare minimum components, we end up with completely illegible (but interesting) experiments like this programming language instead.

Run Linux By Emulating RISC-V On A RISC-V Microcontroller

April 23, 2023 by 7 Comments

For years it was a given that it was impossible to run a Linux based operating system on a less powerful computer whose architecture lacked a memory management unit. There were projects such as uCLinux which sought to provide some tidbits to low computing power Linux users, but ultimately they came to naught. It is achievable after a fashion though, by using the limited architecture to emulate a more powerful one. It’s been done on AVR chips emulating ARM, on ARM chips, and now someone’s done it on an ESP32-C3 microcontroller, a RISC-V part running a RISC-V emulator. What’s going on?

RISC-V is an architecture specification that can be implemented at many levels from a simple microcontroller or even a pile of 74 logic to a full-fat application processor. The ESP32-C3 lies towards the less complicated end of this curve, though that’s not the whole reason for the emulation. The PSRAM storage is used by the C3 as data storage and can’t be used to run software, so to access all that memory capacity an emulator is required that in turn can use the PSRAM as its program memory. It’s a necessary trick for Espressif’s implementation of the architecture.

Surprisingly it’s not as slow as might be expected, with a boot-up time under two minutes. It’s not what we’d expect from our desktop powerhouses, but it’s not so long ago that certain lower-power full-fat processors could be just as lethargic. For past glories, see the AVR running Linux, and the RP2040.

A RISC-V Supercluster For Very Low Cost

April 19, 2023 by 22 Comments

As ARM continues to make inroads in the personal computing space thanks to its more modern and streamlined instruction set architecture (ISA) and its reduced power demands especially compared to x86 machines, the main reason it continues to become more widespread is how easy it is to get a license to make chips using this ISA. It’s still not a fully open source instruction set, though, so if you want something even more easily accessible than ARM you’ll need to find something like these chips running the fully open-source RISC-V ISA and possibly put them to work in a custom supercluster.

[bitluni] recently acquired a large number of CH32V003 microcontrollers and managed to configure them all to work together in a cluster. The entire array is only $2 (not including all of the other components attached to the board) so a cluster of arbitrary size is potentially possible. [bitluni] built a four-layer PCB for this project with an 8-bit bus so the microcontrollers can communicate with each other. Each chip has its own ADC and I/O that are wired to a set of GPIO pins on the sides of the board. The build is rounded out with a USB interface for programming and power.

There were a few quirks to get this supercluster up and running, including some issues with the way the reset and debug pins work on these specific microcontrollers. With some bugs like this out of the way, the entire cluster is up and running, and [bitluni] hints that his design could be easily interfaced with even larger RISC-V superclusters. As for a use for this build, sometimes clusters like these are built just to build them, but since the I/O and ADCs are accessible in theory this cluster could do anything a larger microcontroller might be able to do, only at a much lower price.

Continue reading “A RISC-V Supercluster For Very Low Cost” →

Picture of the miniJen structure on a presentation desk

A Jenkins Demo Stand For Modern Times

March 24, 2023 by 7 Comments

Once you’re working on large-scale software projects, automation is a lifesaver, and Jenkins is a strong player in open-source automation – be it software builds, automated testing or deploying onto your servers. Naturally, it’s historically been developed with x86 infrastructure in mind, and let’s be fair, x86 is getting old. [poddingue], a hacker and a Jenkins contributor, demonstrates that Jenkins keeps up with the times, with a hardware demo stand called miniJen, that has Jenkins run on three non-x86 architectures – arm8v (aarch64), armv7l and RISC-V.

There’s four SBCs of different architectures involved in this, three acting as Jenkins agents executing tasks, and one acting as a controller, all powered with a big desktop PSU from Pine64. The controller’s got a bit beefier CPU for a reason – at FOSDEM, we’ve seen it drive a separate display with a Jenkins dashboard. It’s very much a complete demo for its purpose, and definitely an eyecatcher for FOSDEM attendees passing by the desk! As a bonus, there’s also a fascinating blog post about how [poddingue] got to running Jenkins on RISC-V in particular.

Even software demonstrations get better with hardware, and this stood out no doubt! Looking to build a similar demo, or wondering how it came together? [poddingue] has blog posts on the demo’s structure, a repo with OpenSCAD files, and a trove of videos demonstrating the planning, design and setup process. As it goes with continuous integrations, we’ve generally seen hackers and Jenkins collide when it comes to build failure alerts, from rotating warning lights to stack lights to a Christmas tree; however, we’ve also seen a hacker use it to keep their firmware size under control between code changes. And, if you’re wondering what continuous integration holds for you, here’s our hacker-oriented deep dive.

The Future Of RISC-V And The VisionFive 2 Single Board Computer

March 6, 2023 by 47 Comments

We’ve been following the open, royalty-free RISC-V ISA for a while. At first we read the specs, and then we saw RISC-V cores in microcontrollers, but now there’s a new board that offers enough processing power at a low enough price point to really be interesting in a single board computer. The VisionFive 2 ran a successful Kickstarter back in September 2022, and I’ve finally received a unit with 8 GB of ram. And it works! The JH7110 won’t outperform a modern desktop, or even a Raspberry Pi 4, but it’s good enough to run a desktop environment, browse the web, and test software.

And that’s sort of a big deal, because the RISC-V architecture is starting to show up in lots of places. The challenge has been getting real hardware that’s powerful enough to run Linux and compile software on, that doesn’t cost an arm and a leg. If ARM is an alternative architecture, then RISC-V is still an experimental one, and that is an issue when trying to use the VF2. That’s a theme we’ll repeat a few times, but the thing to remember here is that getting more devices in the wild is the first step to fixing things. Continue reading “The Future Of RISC-V And The VisionFive 2 Single Board Computer” →

Forth Cracks RISC-V

January 8, 2023 by 48 Comments

Over the decades there have been many programming languages, some of which have flowered briefly, and others that have stuck around despite newer, better, and faster competition. Few languages embody this last group more than FORTH, over five decades old and still cropping up wherever a simple, elegant, fast, and compact stack-based programming language fits the bill. [Alexander Williams] has now taken it somewhere new, with a FORTH in RISC-V assembly which runs on the GD32 series of microcontrollers that are RISC-V lookalikes of the popular STM32 ARM parts.

We have to admit to last having used FORTH on an 8-bit home computer in the 1980s, aside from a moment’s idle play on discovering that the Open Firmware on Apple computers is a FORTH interpreter. Thus we’re intrigued by this implementation, but not from a position of FORTH expertise. We’d expect such an efficient language to be extremely quick though, so it’s definitely something to keep an eye on for when a suitable dev board comes our way. If it interests you, take a look at the GitHub repository.

New Part Day: ESP32-P4 Espressif RISC-V Powerhouse

January 7, 2023 by 63 Comments

It seems every day there’s a new microcontroller announcement for which the manufacturer is keen to secure your eyeballs. Today it’s the turn of Espressif, whose new part is the ESP32-P4, which despite being another confusingly named ESP32, is a high-performance addition to their RISC-V line-up.

On board are dual-core 400 MHz and a single-core low power 40 MHz RISC-V processors, and an impressive array of hardware peripherals including display and camera interfaces and a hardware JPEG codec alongside the ones you’d expect from an ESP32 part. It’s got a whopping 768 KB of on-chip SRAM as well as 8 K of very fast cache RAM for intensive operations.

So after the blurb, what’s in it for us? It’s inevitable that the RISC-V parts will over time displace the Tensilica parts over time, so we’ll be seeing more on this processor in upcoming Hackaday projects. We expect in particular for this one to be seized upon by badge developers, who are intent on pushing extra functionality out of their parts.So we look forward to seeing the inevitable modules with this chip on board, and putting them through their paces.

Thanks [Renze] for the tip.