Hackaday Prize Entry: They Make FPGAs That Small?

There are a few development boards entered in this year’s Hackaday Prize, and most of them cover well-tread ground with their own unique spin. There are not many FPGA dev boards entered. Whether this is because programmable logic is somehow still a dark art for solder jockeys or because the commercial offerings are ‘good enough’ is a matter of contention. [antti lukats] is doing something that no FPGA manufacturer would do, and he’s very good at it. Meet DIPSY, the FPGA that fits in the same space as an 8-pin DIP.

FPGAs are usually stuffed into huge packages – an FPGA with 100 or more pins is very common. [antti] found the world’s smallest FPGA. It’s just 1.4 x 1.4mm on a wafer-scale 16-pin BGA package. The biggest problem [antti] is going to have with this project is finding a board and assembly house that will be able to help him.

The iCE40 UltraLite isn’t a complex FPGA; there are just 1280 logic cells and 7kByte of RAM in this tiny square of programmable logic. That’s still enough for a lot of interesting stuff, and putting this into a convenient package is very interesting. The BOM for this project comes out under $5, making it ideal for experiments in programmable logic and education.

A $5 FPGA is great news, and this board might even work with the recent open source toolchain for iCE40 FPGAs. That would be amazing for anyone wanting to dip their toes into the world of programmable logic.

The 2015 Hackaday Prize is sponsored by:

Gates to FPGAs: TTL Electrical Properties

On the path to exploring complex logic, let’s discuss the electrical properties that digital logic signals are comprised of. While there are many types of digital signals, here we are talking about the more common voltage based single-ended signals and not the dual-conductor based differential signals.

Simulated "Real Life"
Single-ended Logic Signal

I think of most logic as being in one of two major divisions as far as the technology used for today’s logic: Bipolar and CMOS. Bipolar is characterized by use of (non-insulated gate) transistors and most often associated with Transistor Transistor Logic (TTL) based logic levels. As CMOS technology came of age and got faster and became able to drive higher currents it began to augment or offer an alternative to bipolar logic families. This is especially true as power supply voltages dropped and the need for low power increased. We will talk more about CMOS in the next installment.

TTL was a result of a natural progression from the earlier Resistor Transistor Logic (RTL) and Diode Transistor Logic (DTL) technologies and the standards used by early TTL became the standard for a multitude of logic families to follow.

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Really, Really Retro Computer On An FPGA

[Daniel Bailey] built himself a scaled-down clone of a very early computer in an FPGA. Specifically, he wrote some VHDL code to describe the machine in question, a scaled-down clone of the Manchester Small-Scale Experimental Machine with an 8-bit processor and a whopping 8 bytes of RAM, all of which are displayed on an LED screen. Too cool.

That he can get it to do anything at all with such constraints amazes us. Watch him program it and put it through its paces in the video below the break.

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Solving Rubik’s Cube With An FPGA

For their final project for ECE 5760 at Cornell, [Alex], [Sungjoon], and [Rameez] are solving Rubik’s Cubes. They’re doing it with an FPGA, with homebrew robot arms to twist and turn a rainbow cube into the correct position.

First, the mechanical portion of the build. The team are using a system of three robot arms positioned on the left, right, and back faces of the cube relative to a camera. When a cube is placed in the jaws of this robot, the NTSC camera data is fed into an FPGA, where a Nios II soft core handles the actual detection of the cube faces, the solver algorithm, and the controller to send servo commands to the robot arms.

The algorithm used for solving the cube is CFOP – solve the white cross, the white corners, the middle layer, the top face, and finally the entire cube. In practice, the robot ended up taking between 60-70 moves. This is not the most efficient algorithm; the Thistethwaite algorithm only requires 52 moves. There’s a reason for this apparent inefficiency – the Thistlethwaite algorithm requires large look-up tables.

Once the cube is scanned and the correct moves are computed, the soft core in sends commands out through the FPGA’s GPIO pins. Each cube can be solved in under three minutes after it has been scanned, but the team ran into problems with scanning accuracy. It’s a problem that can be fixed with the right lighting setup and better aberrant cubie detection, and a great final project using FPGAs.

Video demo below.

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An Open Source Toolchain For iCE40 FPGAs

FPGAs are great, but open source they are not. All the players in FPGA land have their own proprietary tools for creating bitstream files, and synthesizing the HDL of your choice for any FPGA usually means agreeing to terms and conditions that nobody reads.

After months of work, and based on the previous work of [Clifford Wolf] and [Mathias Lasser], [Cotton Seed] has released a fully open source Verilog to bitstream development tool chain for the Lattice iCE40LP with support for more devices in the works.

Last March, we saw the reverse engineering of the Lattice ICE40 bitstream, but this is a far cry from a robust, mature development platform. Along with Yosys, also written by [Clifford Wolf] it’s relatively simple to go from Verilog to an FPGA that runs your own code.

Video demo below, and there’s a ton of documentation over on the Project IceStorm project page. You can pick up the relevant dev board for about $22 as well.

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From Gates to FPGA’s – Part 1: Basic Logic

It’s time to do a series on logic including things such as programmable logic, state machines, and the lesser known demons such as switching hazards. It is best to start at the beginning — but even experts will enjoy this refresher and might even learn a trick or two. I’ll start with logic symbols, alternate symbols, small Boolean truth tables and some oddball things that we can do with basic logic. The narrative version is found in the video, with a full reference laid out in the rest of this post.


1The most simple piece of logic is inversion; making a high change to low or a low change to high. Shown are a couple of ways to write an inversion including the ubiquitous “bubble” that we can apply almost anywhere to imply an inversion or a “True Low”. If it was a one it is now a zero, where it was a low it is now a high, and where it was true it is now untrue.


2Moving on to the AND gate we see a simple truth table, also known as a Boolean Table, where it describes the function of “A AND B”. This is also our first opportunity to see the application of an alternate symbol. In this case a “low OR a low yields a low”


3Most if not all of the standard logic blocks come in an inverted form also such as the NAND gate shown here. The ability to invert logic functions is so useful in real life that I probably used at least three times the number of NAND gates as regular AND gates when doing medium or larger system design. The useful inversion can occur as spares or in line with the logic.

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Dancing Mandelbrot Set on a FPGA

This FPGA based build creates an interesting display which reacts to music. [Wancheng’s] Dancing Mandelbrot Set uses an FPGA and some math to generate a controllable fractal display.

The build produces a Mandelbrot Set with colours that are modified by an audio input. The Terasic DE2-115 development board, which hosts a Cyclone IV FPGA, provides all the IO and processing. On the input side, UART or an IR remote can be used to zoom in and out on the display. An audio input maps to the color control, and a VGA output allows for the result to be displayed in real time.

Dancing Mandelbrot Block DiagramOn the FPGA, a custom calculation engine, running at up to 150 MHz, does the math to generate the fractal. A Fast Fourier transform decomposes the audio input into frequencies, which are used to control the colors of the output image.

This build is best explained by watching, so check out the video after the break.

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