RISC-V

103 Articles

Arduino Code? On My 8051? It’s More Likely Than You Think

March 22, 2026 by 29 Comments

The 8051 was an 8-bit Harvard-architecture microcontroller first put out by Intel in 1980.  They’ve since discontinued that line, but it lives on in the low-cost STC8 family of chips, which is especially popular in Asia. They’re cheap as, well, chips — under 1$ — but lack compatibility with modern toolchains. If you’re happy with C, then you’re fine, but if you want to plus-plus it up and use all those handy-dandy shortcuts provided by the Arduino ecosystem, you’re out of luck. Or rather, you were, until [Bùi Trịnh Thế Viên] aka [thevien257] came up with a workaround.

The workaround is delightfully Hack-y. One could, conceivably, port a compiler for Arduino’s  Wiring to the 8051, but that’s not what [Viên] did, probably because that would be a lot of work. There isn’t even a truly modern toolchain to put plain C on this chip. Instead, [Viên] started with rv51, a RISC-V emulator written in 8051 assembly language by [cryozap]. RISC-V is a lot easier to work with and, frankly, a more useful skill to build up.

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WCH CH32M030: Another Microcontroller To Watch Out For

January 16, 2026 by 49 Comments

One of the joys of writing for Hackaday comes in following the world of new semiconductor devices, spotting interesting ones while they are still just entries on manufacturer websites, and then waiting for commonly-available dev boards. With Chinese parts there’s always a period in which Chinese manufacturers and nobody else has them, and then they quietly appear on AliExpress.

All of which brings us to the WCH CH32M030, a chip that’s been on the radar for a while and has finally broken cover. It’s the CH32 RISC-V microcontroller you may be familiar with, but with a set of four half-bridge drivers on board for running motors. A handy, cheap, and very smart motor controller, if you will.

There’s been at  least one Chinese CH32M030 dev board (Chinese language) online for a while now, but the one listed on AliExpress appears to be a different design. At the time of writing the most popular one is still showing fewer than 20 sales, so we’re getting in at the ground floor here.

We think this chip is of interest because it has the potential to be used in low price robotic projects, replacing as it does a couple of parts or modules in one go. If you use it, we’d like to hear from you!

World’s Cheapest ARM Debugger Is Actually RISC-V

October 22, 2025 by 18 Comments

[bogdanthegeek] has a lot of experience with the ARM platform, and their latest escapade into working with cheap ARM chips recovered from disposable vapes involved a realization that it was just plain wrong to debug such recovered silicon with something as expensive as a Pi Pico. No, they needed to build a debugger using the super cheap CH32V003.

What follows is an interesting tour around ARM Debug Access Port (DAP) programmers and creating a practical USB-connected device that actually works with modern toolchains. The first problem to be solved was that of host connectivity. These days, it’s USB or go home, which immediately limits the microcontrollers you can choose. Luckily for [Bogdan], they were aware of the excellent work by [cnlohr] on wedging low-speed USB support onto the RISC-V CH32v003 with the software-only bit-banging rv003usb, which provided a starting point. The next issue was to check for interrupt-driven endpoint support (needed for low-speed USB) in the Mac OS X kernel, which they knew was being dropped at an alarming rate (well, at least for full-speed). Luckily, the CMSIS-DAP standard required support for interrupt-driven USB endpoints, so kernel support was likely intact.

Next, [Bogdan] noticed that the DAPLink project had been ported to the bigger, native-USB WCH chips like the CH32V203, so it was a matter of porting this code to the diminutive CH32V003 using the rv003usb stack for the USB support using [cnlohr]’s ch32fun toolchain. There were a few bumps along the way with a lack of clarity in the DAPLink code, and some inconsistencies (across platforms) with the USB library dependencies of the upstream tool pyOCD, but they did get some tools working on at least Mac OS and some others on Linux. Which was nice.

We’ve covered the CH32V003 a fair bit, with people trying to give it all kinds of big-CPU tricks, such as speech recognition (of sorts) or even building a supercluster.

160-core RISC V Board Is The M.2 CoProcessor You Didn’t Know You Needed

July 7, 2025 by 20 Comments

Aside from GPUs, you don’t hear much about co-processors these days. [bitluni] perhaps missed those days, because he found a way to squeeze a 160 core RISC V supercluster onto a single m.2 board, and shared it all on GitHub.

OK, sure, each core isn’t impressive– he’s using CH32V003, so each core is only running at 48 MHz, but with 160 of them, surely it can do something? This is a supercomputer by mid-80s standards, after all.  Well, like anyone else with massive parallelism, [bitluni] decided to try a raymarcher. It’s not going to replace RTX anytime soon, but it makes for a good demo.

Like his previous m.2 project, an LED matrix,  the cluster is communicating over PCIe via a WCH CH382 serial interface. Unlike that project, blinkenlights weren’t possible: the tiny, hair-thin traces couldn’t carry enough power to run the cores and indicator LEDs at once. With the power issue sorted, the serial interface is the big bottleneck. It turns out this cluster can crunch numbers much faster than it can communicate. That might be a software issue, however, as the cluster isn’t using all of the CH382’s bandwidth at the moment. While that gets sorted there are low-bandwidth, compute-heavy tasks he can set for the cluster. [bitluni] won’t have trouble thinking of them; he has a certain amount of experience with RISCV microcontroller clusters.

We were tipped off to this video by [Steven Walters], who is truly a prince among men. If you are equally valorous, please consider dropping informational alms into our ever-present tip line. 

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A RISC-V Operating System Instruction Manual

May 26, 2025 by 1 Comment

To some, an operating system is a burden or waste of resources, like those working on embedded systems and other low-power applications. To others it’s necessary, abstracting away hardware so that higher-level programming can be done. For most people it’s perhaps not thought of at all. But for a few, the operating system is the most interesting piece of software running on a computer and if you’d like to investigate what makes this often overlooked aspect of computer science interesting, take a look at this course on operating systems from Cornell University.

The operating system itself is called Earth and Grass Operating System because it splits the functionality of the operating system into three separate parts. The Earth layer involves dealing with hardware, the Grass layer involves hardware-independent aspects, and a third application layer implements other key operating system features. It’s built for a RISC-V processor, since that instruction set is completely open source and transparent about what it’s doing. It’s also incredibly small, coming in at around 2000 lines of code. The course covers nine areas, with the first six being core operating system functions and the remaining three covering more advanced operating system concepts.

For understanding the intricacies and sometimes mysterious ways that operating systems work, a course like this can go a long way into unraveling those mysteries and developing a deeper understanding of how it brings the hardware to work for higher-level software. We actually featured this operating system two years ago, before this course was created, which covers this project for those who like to take a more self-directed approach, or simply want a lightweight OS for a RISC-V system.

Kaleidoscopico Shows Off Pi Pico’s Capabilities

April 27, 2025 by 14 Comments

In the early days of computing, and well into the era where home computers were common but not particularly powerful, programming these machines was a delicate balance of managing hardware with getting the most out of the software. Memory had to be monitored closely, clock cycles taken into account, and even video outputs had to be careful not to overwhelm the processor. This can seem foreign in the modern world where double-digit gigabytes of memory is not only common, it’s expected, but if you want to hone your programming skills there’s no better way to do it than with the limitations imposed by something like a retro computer or a Raspberry Pi Pico.

This project is called Kaleidoscopio, built by [Linus Åkesson] aka [lft] and goes deep into the hardware of the Pi Pico in order to squeeze as much out of the small, inexpensive platform as possible. The demo is written with 17,000 lines of assembly using the RISC-V instruction set. The microcontroller has two cores on it, with one core acting as the computer’s chipset and the other acts as the CPU, rendering the effects. The platform has no dedicated audio or video components, so everything here is done in software using this setup to act as a PC from the 80s might. In this case, [lft] is taking inspiration from the Amiga platform, his favorite of that era.

The only hardware involved in this project apart from the Pi Pico itself are a few resistors, an audio jack, and a VGA port, further demonstrating that the software is the workhorse in this build. It’s impressive not only for wringing out as much as possible from the platform but for using the arguably weaker RISC-V cores instead of the ARM cores, as the Pi Pico includes both. [lft] goes into every detail on the project’s page as well, for those who are still captivated by the era of computer programming where every bit mattered. For more computing demos like this, take a look at this one which is based on [lft]’s retrocomputer of choice, the Amiga.

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Checking In On The ISA Wars And Its Impact On CPU Architectures

March 18, 2025 by 33 Comments

An Instruction Set Architecture (ISA) defines the software interface through which for example a central processor unit (CPU) is controlled. Unlike early computer systems which didn’t define a standard ISA as such, over time the compatibility and portability benefits of having a standard ISA became obvious. But of course the best part about standards is that there are so many of them, and thus every CPU manufacturer came up with their own.

Throughout the 1980s and 1990s, the number of mainstream ISAs dropped sharply as the computer industry coalesced around a few major ones in each type of application. Intel’s x86 won out on desktop and smaller servers while ARM proclaimed victory in low-power and portable devices, and for Big Iron you always had IBM’s Power ISA. Since we last covered the ISA Wars in 2019, quite a lot of things have changed, including Apple shifting its desktop systems to ARM from x86 with Apple Silicon and finally MIPS experiencing an afterlife in  the form of LoongArch.

Meanwhile, six years after the aforementioned ISA Wars article in which newcomer RISC-V was covered, this ISA seems to have not made the splash some had expected. This raises questions about what we can expect from RISC-V and other ISAs in the future, as well as how relevant having different ISAs is when it comes to aspects like CPU performance and their microarchitecture.

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