FPGA

387 Articles

Programming A RISC-V Softcore With Ada

October 8, 2018 by 9 Comments

We were contacted by [morbo] to let us know about a project on the AdaCore blog that concerns programming a PicoRV32 RISC-V softcore with Ada. The softcore itself runs on a Lattice ICE40LP8K-based TinyFPGA-BX FPGA board, which we have covered in the past.

The blog post describes how to use the Community edition of the GNAT Ada compiler to set up the development environment, before implementing a simple example project that controls a strip of WS28212b RGB LED modules. There are two push buttons changing the animation and brightness of the lights.

The source can be found at the author’s Github repository, and contains both the Ada source and the Verilog source for the PicoRV32 softcore. To build the project one needs the GNAT compiler, as well as the open-source iCE40 development tools to compile the softcore.

There is a video demonstrating the finished example project, that we’ve placed below the break.

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Easy FPGA CPU With MAX1000

October 5, 2018 by 8 Comments

Ok, we’ll admit it. We like FPGAs because it reminds us of wiring up a 100-in-1 kit when we were kids. But the truth is, many projects are just as well off to have a CPU. But there’s a real sweet spot when you have a CPU and an FPGA together. Intel (or Altera, if you prefer) has the NIOS II CPU core, but that’s hard to configure, right? Maybe not, thanks to a project by [jefflieu] over on GitHub. He’s assembled some basic definitions and libraries to easily — relatively speaking — use NIOS II on the MAX1000 as well as a few other boards. The MAX1000 is a pretty nice board for about $30, so this is a very inexpensive way to get into “System on Chip” (SOC) development.

[jeff] goes into more detail in a blog post, but the idea is pretty simple. We tried it, and it works very well, although we found a few things hard to follow so read on to see how we managed.

The idea behind SoC development is you define your CPU configuration and then your hardware devices. Then you write software to talk to those custom hardware devices and — of course — write your actual application code. So you don’t just write a program, you also define the CPU the program will run on and the hardware that it will talk to.

There are several ready-to-go I/O devices included in the project, but the real fun will be writing your own. The Intel tools have the C compiler and everything else you need. You could also do everything from scratch, but these tools make it much easier to get started.

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Icestorm Tools Roundup: Open Source FPGA Dev Guide

October 3, 2018 by 7 Comments

We like the ICE40 FPGA from Lattice for two reasons: there are cheap development boards like the Icestick available for it and there are open source tools. We’ve based several tutorials on the Icestorm toolchain and it works quite well. However, the open source tools don’t always expose everything that you see from commercial tools. You sometimes have to dig a little to find the right tool or option.

Sometimes that’s a good thing. I don’t need to learn yet another fancy IDE and we have plenty of good simulation tools, so why reinvent the wheel? However, if you are only using the basic workflow of Yosys, Arachne-pnr, icepack, and iceprog, you could be missing out on some of the most interesting features. Let’s take a deeper look.

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Free ARM Cores For Xilinx FPGAs

October 2, 2018 by 30 Comments

In a surprising move, ARM has made two Cortex-M cores available for FPGA development at no cost.

In the over three decades since [Sophie Wilson] created the first ARM processor design for the Acorn Archimedes home computer, the architecture has been managed commercially such that it has become one of the most widely adopted on the planet. From tiny embedded microcontrollers in domestic appliances to super-powerful 64-bit multi-core behemoths in high-end mobile phones, it’s certain you’ll own quite a few ARM processors even if you don’t realise it. Yet none of those processors will have been made by ARM, instead the Cambridge-based company will have licenced the intellectual property of their cores to another semiconductor company who will manufacture the device around it to their specification. ARM core licences cost telephone-number sums, so unless you are a well-financed semiconductor company, until now you probably need not apply.

You will still have to shell out the dough to get your hands on a core for powerful chips like those smartphone behemoths, but if your tastes are more modest and run only to a Cortex M1 or M3 you might be in luck. For developers on Xilinx FPGAs they have extended the offer of those two processor cores at zero cost through their DesignStart Programme.

It’s free-as-in-beer rather than something that will please open-source enthusiasts, But it’s certainly a fascinating development for experimenters who want to take ARM for a spin on their own gate array. Speculation is swirling that this is a response to RISC-V, but we suspect it may be more of a partial lifting of the skirts to entice newbie developers such as students or postgraduates. If you arrive in the world of work already used to working with ARM IP at the FPGA level then you are more likely to be on their side of the fence when those telephone-number deals come up.

Thanks [Rik] for the tip!

ICEstick Makes Terrible Radio Transmitter

September 30, 2018 by 13 Comments

We’ve done a lot of posts on how to use the Lattice iCEstick ranging from FPGA tutorials to how to use one as a logic analyzer. If you picked up one of these inexpensive boards here’s a fun little experiment. [T4D10N] saw a project [Hamster] put together to send SOS on the FM radio band using nothing but an FPGA. [Hamster used a Spartan], so he decided to do the same trick using an iCEstick with the open source IceStorm tools.

You might be surprised that the whole thing only takes 53 lines of Verilog — less if you cut out comments and whitespace. That’s because it uses the FPGA’s built-in PLL to generate a fast clock and then uses a phase accumulator divider to produce three frequencies on the FM radio band; one for a carrier and two for a tone, spaced 150 Hz apart. The result is really frequency shift keying but you can hear the results on an FM radio.

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FPGA Jacked Into Pinball Machine Masters High Scores

September 28, 2018 by 13 Comments

How do you preserve high scores in an old arcade cabinet when disconnecting the power? Is it possible to inject new high scores into a pinball machine? It was the b-plot of an episode of Seinfield, so it has to be worth doing, leading [matthew venn] down the rabbit hole of FPGAs and memory maps to create new high scores in a pinball machine.

The machine in question for this experiment is Doctor Who from Williams, which, despite being a Doctor Who pinball machine isn’t that great of a machine. Still, daleks. This machine is powered by a Motorola 68B09E running at 2MHz, with 8kB of RAM at address 0x0000. This RAM backed up with a few AA batteries, and luckily is in a DIP socket, allowing [matthew] to fab a board loaded up with an FPGA development board that goes between the CPU and RAM.

The basic technique for intercepting and writing a new high score for this pinball machine comes from the incredible [sprite_tm] who is tweeting high scores from a 1943 cabinet. The idea is simple: just have an FPGA look at one specific memory address, and send some data to a computer when the data at that address is updated. For the Doctor Who pinball machine, this is slightly harder than it sounds: the data isn’t stored in hex, but packed BCD. After a little bit of work, though, [matthew] was able to write new high scores from a Python script running on a laptop. All the code (and a few more details) are over on a Github

Extending arcade games by tapping into address and data lines isn’t something we see a lot of, but it has been done, most famously with the Church of Robotron. Here, a few MAME hacks turn a game of Robotron into a Church for the faithful to fully commit themselves to the savior of the world, due to arrive in 66 years and save the remaining humans from the robot apocalypse. This hack of a Doctor Who pinball machine goes beyond a modded version of MAME, and if we’re ever going to make a real chapel with a real game of Robotron, these are the techniques we’re going to use.

Three Part Deep Dive Explains Lattice ICE40 FPGA Details

September 27, 2018 by 15 Comments

It is no secret that we like the Lattice iCE40 FPGA. It has a cheap development board and an open source toolchain, so it is an easy way to get started developing low-cost, low-power FPGA designs. There are a few members of the family that have similar characteristics including the top-of-the-line UltraPlus. [Steve] from Lattice and [Michael Klopfer] from the University of California Irvine have a three-part video series that explain the architecture of the devices. Altogether, the videos are about an hour long and — of course — they use the official tools, not IceStorm. But it is still a great time investment if you have an iCE40 board and you want to understand what the chip has under the hood.

The first part is fairly short and talks a lot about applications. There’s also a nod to the hobbyist use of FPGAs. Keep in mind that the iCE40 FPGAs come in different sizes and variants, so don’t get excited when you see them mention a RISC-V — that isn’t going to fit in your iCEStick, that we know of. The iCEstick has a HX-1K onboard, which is the high-performance variant with 1,280 logic elements, as opposed to the low-power (LP) version.

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