fpga

533 Articles

A Full Stack GPS Receiver

May 9, 2017 by 70 Comments

The usual way of adding GPS capabilities to a project is grabbing an off-the-shelf GPS module, plugging it into a UART, and reading the stream of NMEA sentences coming out of a serial port. Depending on how much you spend on a GPS module, this is fine: the best modules out there start up quickly, and a lot of them recognize the logical AND in ITAR regulations.

For [Mike], grabbing an off-the-shelf module is out of the question. He’s building his own GPS receiver from the ground up using a bit of hardware and FPGA hacking. Already he’s getting good results, and he doesn’t have to futz around with those messy, ‘don’t build ballistic missiles’ laws.

The hardware for this build includes a Kiwi SDR ‘cape’ for the BeagleBone and a Digilent Nexus-2 FPGA board. The SDR board captures raw 1-bit samples taken at 16.268 MHz, and requires a full minute’s worth of data to be captured. That’s at least 120 Megabytes of data for the FPGA to sort through.

The software for this project first acquires the GPS signal by finding the approximate frequency and phase. The software then locks on to the carrier, figures out the phase, and receives the 50bps ‘NAV’ message that’s required to find a position solution for the antenna’s location. The first version of this software was exceptionally slow, taking over 6 hours to process 200 seconds of data. Now, [Mike] has improved the channel tracking code and made it 300 times faster. That’s real-time processing of GPS data, using commodity off-the-shelf hardware. All the software is available on the Gits, making this a project that can very easily be replicated by anyone. We would expect the US State Department or DOD to pay [Mike] a visit shortly.

Of course, this isn’t the first time someone has built a GPS receiver from scratch. A few years ago, less than 1-meter accuracy was possible with an FPGA and a homebrew RF board.

Phase Modulation With An FPGA

May 6, 2017 by 29 Comments

There are two radio modulation schemes everyone should know. Amplitude modulation changes the amplitude — or ‘volume’, if you will — of a carrier frequency and turns all radio into channels owned and operated by a church. Frequency modulation changes the pitch of a carrier frequency and is completely run by Clear Channel. Amateur radio operators are familiar with dozens of other modulation schemes, but there’s one hardly anyone touches. Phase modulation is weird and almost unheard of, but that doesn’t mean you can’t implement it on an FPGA. [nckm] is transmitting audio using phase modulation on an FPGA (Russian, here’s the Google Translatrix).

This hardware is just an Altera MAX10 board, with a single input used for serial data of the audio to be transmitted, and two outputs, each connected to a few bits of wire for a quarter-wave antenna. No, there’s no output filter or anything else except for a few bits of wire. It’s an experiment, chillax.

The Verilog for this project receives an audio signal as serial data in mono, 22050 BPS, 8-bit unsigned samples. These samples are fed into a dynamic PLL with phase shift in the FPGA. Shifting the phases also changes the frequency, so [nckm] can receive this audio signal with the FM transmitter on his phone.

Is this really phase modulation if it’s being received by an FM radio? Eh, maybe. PM and FM are closely related, but certainly distinguishable as modulation schemes in their own right. You can grab [nckm]’s code over on the gits, or check out the video demo below.

Continue reading “Phase Modulation With An FPGA” →

Learn By Fixing: Another Verilog CPU

May 5, 2017 by 17 Comments

Because I often work with students, I’m always on the look-out for a simple CPU, preferably in Verilog, in the Goldilocks zone. That is, not too easy and not too hard. I had high hopes for this 16-bit RISC processor presented by [fpga4student], but without some extra work, it probably isn’t usable for its intended purpose.

The CPU itself is pretty simple and fits on a fairly long web page. However, the details about it are a bit sparse. This isn’t always a bad thing. You can offer students too much help. Then again, you can also offer too little. However, what was worse is one of the modules needed to get it to work was missing! You might argue it was an exercise left to the reader, but it probably should have been pointed out that way.

At first, I was ready to delete the bookmark and move on. Then I decided that the process of fixing this design and doing a little analysis on it might actually be more instructive than just studying a fully working design. So I decided to share my fix with you and look inside the architecture a bit more. On top of that, I’ll show you how to get the thing to run in an online simulator so you can experiment with no software installation. Of course, if you are comfortable with a Verilog toolchain (like the ones from Xilinx or Altera, or even free ones like Icarus or CVer) you should have no problem making that work, either. This time I’ll focus on how the CPU works and next time I’ll show you how to simulate it with some free tools. Continue reading “Learn By Fixing: Another Verilog CPU” →

MATLAB And Simulink For Zynq

May 5, 2017 by 13 Comments

Although we see a lot of MATLAB use in industry and in academia, it isn’t as popular in the hacker community. That’s probably due to the cost. If you’ve ever wondered why companies will pay over $2000 for the base product, you might enjoy the video of a webinar covering using MATLAB and Simulink (a companion product) to program the CPU and FPGA on a Zynq Zedboard. Not interested because of the price? If you aren’t using it for commercial purposes, it isn’t as bad as you think.

MathWorks is one of those companies that likes to market by virtually giving away products to students with the hope that they’ll adopt the same tools when they land jobs in industry. Their flagship product, MATLAB, is well-entrenched in the labs and offices of big corporations. We’ve often thought that MATLAB is sort of what FORTRAN would look like if it had been developed in the last 20 years instead of 60 years ago. It is true that a base license for MATLAB is over $2000. However, if you aren’t using it for commercial purposes, and you can’t score a student license, you can get a personal license of MATLAB for about $150. The extra modules are also similarly reduced in price. If you are a student, the price drops to about $100, although many schools have licenses students can use at no cost to them.

If you watch the video from [Noam Levine], you’ll see you get your money’s worth. If you are wanting to configure the FPGA directly, this isn’t for you. But if you just want to accelerate a program by pushing DSP or other algorithms that can benefit from hardware assistance, MATLAB makes it very easy.

Continue reading “MATLAB And Simulink For Zynq” →

FPGAs In C With Cynth

April 26, 2017 by 30 Comments

Programming an FPGA with Verilog looks a lot like programming. But it isn’t, at least not in the traditional sense. There have been several systems that aim to take C code and convert it into a hardware description language. One of these, cynth, is simple to use and available on GitHub. You will need to install scala and a build system called sbt, if you want to try it.

There are limitations, of course. If you want a preprocessor, you’ll have to run it separately. You can’t use global variables, multiplication, floats, and many other pieces of C. The compiler generates a Verilog file for each C function.
Continue reading “FPGAs In C With Cynth” →

E-ink Display Driven DIY

April 20, 2017 by 44 Comments

E-ink displays are awesome. Humans spent centuries reading non-backlit devices, and frankly it’s a lot easier on the eyes. But have you looked into driving one of these critters yourself? It’s a nightmare. So chapeau! to [Julien] for his FPGA-based implementation that not only uses our favorite open-source FPGA toolchain, and serves as an open reference implementation for anyone else who’s interested.

Getting just black and white on an E-ink display is relatively easy — just hit the ink pixels with the same signal over and over until they give up. Greyscale is made by applying much more nuanced voltages because the pixels are somewhat state-dependent. If the desired endpoint is a 50% grey, for instance, you’d hit it with a different pulse train if the pixel were now white versus if it were now black. (Ever notice that your e-book screen periodically does a white-black flash? It’s resetting all the pixels to a known state.) And that’s not even taking into account the hassles with the various crazy voltages that E-ink displays require, which [Julien] wisely handed off to a dedicated chip.

In the end, the device has to make 20-50 passes through the screen for one user-visible refresh. [Julien] found that the usual microcontrollers just weren’t capable of the speed that he wanted, hence the FPGA and custom waveform tables. We’ve seen E-ink hacks before, and [Julien] is standing on the shoulders of giants, most notably those of [Petteri Aimonen] and [Sprite_tm]. [Julien]’s hack has the fastest updates we’ve ever seen.

We still can’t wait for the day that there is a general-purpose E-ink driver chip out there for pennies, because nearly every project we make with a backlit display would look better, and chew through the batteries slower, with E-ink. In the meantime, [Julien]’s FPGA implementation is pretty close, and it’s fully open.

Continue reading “E-ink Display Driven DIY” →

Lattice ICE40 FPGA Configured By Linux Kernel

April 13, 2017 by 15 Comments

The Linux kernel recently added support for loading firmware into an FPGA via the FPGA Manager Framework. [OpenTechLab] has built a driver for the Lattice iCE40 FPGA (same chip used on the iCEStick and other development boards). One attraction to the iCE40 is there is an open source toolchain called iCEStorm.

Even if you aren’t specifically interested in FPGAs, the discussion about Linux device drivers is good background. The principles would apply to other drivers, and would definitely apply if you want to write another FPGA loader.

Continue reading “Lattice ICE40 FPGA Configured By Linux Kernel” →