A RISC-V That The Rest Of Us Can Understand

February 9, 2018 by Jenny List 32 Comments

There is great excitement in the world of microprocessors, surrounding the RISC-V architecture. This is an open source modular instruction set specification that has seen implementations on FPGAs, and is starting to emerge in dedicated silicon.

If you are not yet up to speed on what is probably going to be the most important microprocessor development of a generation, you should watch this video. As [Robert Baruch] sets out to demonstrate, the combination of RISC technology and a modular instruction set means that the simplest processor compliant with the RISC-V specification can be surprisingly accessible. And to demonstrate this he’s building one from LSI and MSI ~~TTL~~ CMOS chips, something we’d more usually expect to see in a recreation of a much older architecture.

The video below the break is the first of a forthcoming series, and in it he introduces the project and gives us an easily-understandable overview of RISC-V before explaining the mechanics of a register for his RISC-V implementation. This will be his first module, and he’s created a PCB for it. He runs through its design, his choice of indicator LEDs, and then his choice of PCB house. There is also a breakout board, with two of the PCI sockets he’ll be using for his backplane. Finally we see the board being tested, with LEDs lighting up in response to values being stored in a completed register.

[Robert] has appeared on these pages many times before, among the most recent with his TMS9900-based breadboard computer. This build moves away from his retro fare though, and should be well worth watching for future installments.

Continue reading “A RISC-V That The Rest Of Us Can Understand” →

Simulating The Learn-by-Fixing CPU

May 12, 2017 by Al Williams 24 Comments

Last time I looked at a simple 16-bit RISC processor aimed at students. It needed a little help on documentation and had a missing file, but I managed to get it to simulate using a free online tool called EDA Playground. This time, I’ll take you through the code details and how to run the simulation.

You’ll want to refer to the previous post if you didn’t read it already. The diagrams and tables give a high-level overview that will help you understand the files discussed in this post.

If you wanted to actually program this on a real FPGA, you’d have a little work to do. The memory and register initialization is done in a way that works fine for simulation, but wouldn’t work on a real FPGA. Anyway, let’s get started!

Continue reading “Simulating The Learn-by-Fixing CPU” →

Learn By Fixing: Another Verilog CPU

May 5, 2017 by Al Williams 17 Comments

Because I often work with students, I’m always on the look-out for a simple CPU, preferably in Verilog, in the Goldilocks zone. That is, not too easy and not too hard. I had high hopes for this 16-bit RISC processor presented by [fpga4student], but without some extra work, it probably isn’t usable for its intended purpose.

The CPU itself is pretty simple and fits on a fairly long web page. However, the details about it are a bit sparse. This isn’t always a bad thing. You can offer students too much help. Then again, you can also offer too little. However, what was worse is one of the modules needed to get it to work was missing! You might argue it was an exercise left to the reader, but it probably should have been pointed out that way.

At first, I was ready to delete the bookmark and move on. Then I decided that the process of fixing this design and doing a little analysis on it might actually be more instructive than just studying a fully working design. So I decided to share my fix with you and look inside the architecture a bit more. On top of that, I’ll show you how to get the thing to run in an online simulator so you can experiment with no software installation. Of course, if you are comfortable with a Verilog toolchain (like the ones from Xilinx or Altera, or even free ones like Icarus or CVer) you should have no problem making that work, either. This time I’ll focus on how the CPU works and next time I’ll show you how to simulate it with some free tools. Continue reading “Learn By Fixing: Another Verilog CPU” →

The Gray-1, A Computer Composed Entirely Of ROM And RAM

February 2, 2017 by Jenny List 52 Comments

When we learn about the internals of a microprocessor, we are shown a diagram that resembles the 8-bit devices of the 1970s. There will be an ALU, a program counter, a set of registers, and address and data line decoders. Most of us never go significantly further into the nuances of more modern processors because there is no need. All a processor needs to be is a black box, unless it has particularly sparked your interest or you are working in bare-metal assembly language.

We imagine our simple microprocessor as built from logic gates, and indeed there have been many projects on these pages that create working processors from piles of 74 series chips. But just occasionally a project comes along that reminds us there is more than one way to build a computer, and our subject today is just such a moment. [Olivier Bailleux] has created his “Gray-1”, a processor whose only active components are memory chips, both ROM and RAM.

The clever part comes with the descriptions of how the ROMs are used to recreate the different functions of the processor, through careful programming. Some functions such as registers for example use loops, in which some of the address lines are driven from the data lines to maintain the ROM at a set location. The name of the computer comes from its program counter, which counts in Gray code.

The full processor implements a RISC architecture, and there is a simulator to allow code development without a physical unit. The write-up is both comprehensive and accessible, and makes a fascinating read.

It’s safe to say this is the only processor we’ve seen with this novel approach to architecture. Some more conventional previous features though have been an effort to create a processor entirely from NAND gates, and another made from 74 logic.

The Cardboard Computer

January 18, 2017 by Anool Mahidharia 37 Comments

Every time we say “We’ve seen it all”, along comes a project that knocks us off. 60 year old [Mark Nesselhaus] likes to learn new things and he’s never worked with hardware at the gate level. So he’s building himself a 4-bit Computer, using only Diode-Transistor Logic. He’s assembling the whole thing on “card board” perf-board, with brass tacks for pads. Why — because he’s a thrifty guy who wants to use what he has lying around. Obviously, he’s got an endless supply of cardboard, tacks and Patience. The story sounds familiar. It started out as a simple 4-bit full adder project and then things got out of hand. You know he’s old school when he calls his multimeter an “analog VOM”!

It’s still work in progress, but he’s made a lot of it in the past year. [Mark] started off by emulating the 4-bit full adder featured on Simon Inns’ Waiting for Friday blog. This is the ALU around which the rest of his project is built. With the ALU done, he decided to keep going and next built a 4-to-16 line decoder — check out the thumbnail image to see the rats nest of jumbled wires. Next on his list were several flip flops — R-S, J-K and D types, which would be useful as program counters. This is when he bumped into problems with signal levels, timing and triggering. He decided to allow himself the luxury of adding one IC to his build — a 555 based clock generator. But he still needed some pulse shaping circuitry to make it work consistently.

from right, Input, +5V, nc, gnd — LED Driver : from left, Gnd, NC, +5V, Input

[Mark] also built a finite-state-machine sequencer based on the work done by Rory Mangles TinyTim project. He finished building some multiplexers and demultiplexers, and it appears he may be using a whole bank of 14 wall switches for address, input and control functions. For the output display, he assembled a panel using LED’s recovered from a $1 Christmas light string. Something seems amiss with his LED driver, though — 2mA with LED on and >2.5mA with LED off. The LED appears to be connected across the collector and emitter of the PNP transistor. Chime in with your comments.

This build seems to be shaping along the lines of the Megaprocessor that we’ve swooned over a couple of times in the past. Keep at it, [Mark]!

Continue reading “The Cardboard Computer” →

HiFive1: RISC-V In An Arduino Form Factor

November 29, 2016 by Brian Benchoff 29 Comments

The RISC-V ISA has seen an uptick in popularity as of late — almost as if there’s a conference going on right now — thanks to the fact that this instruction set is big-O Open. This openness allows anyone to build their own software and hardware. Of course, getting your hands on a RISC-V chip has until now, been a bit difficult. You could always go over to opencores, grab some VHDL, and run a RISC-V chip on an FPGA. Last week, OnChip released the RISC-V Open-V in real, tangible silicon.

Choice is always a good thing, and now SiFive, a fabless semiconductor company, has released the HiFive1 as a crowdfunding campaign on CrowdSupply. It’s a RISC-V microcontroller, completely open source, and packaged in the ever so convenient Arduino form factor.

The heart of the HiFive1 is SiFive’s FE310 SoC, a 32-bit RISC-V core running at 320+ MHz. As far as peripherals go, the HiFive1 features 19 digital IO pins, one SPI controller, 9 PWM pins, an external 128Megabit Flash, and five volt IO. Performance-wise, the HiFive1 is significantly faster than the Intel Curie-powered Arduino 101, or the ARM Cortex M0+ powered Arduino Zero. According to the crowdfunding campaign, support for the Arduino IDE is included. A single HiFive1 is available for $59 USD.

Since this is an Open Source chip, you would expect everything about it to be available. SiFive has everything from the SDK to the RTL available on GitHub. This is an impressive development in the ecosystem of Open Hardware, and something we’re going to take a look at when these chips make it out into the world.

RISC, Tagged Memory, And Minion Cores

December 21, 2014 by Brian Benchoff 23 Comments

Buy a computing device nowadays, and you’re probably getting something that knows x86 or an ARM. There’s more than one architecture out there for general purpose computing with dual-core MIPS boards available and some very strange silicon that’s making its way into dev boards. lowRISC is the latest endeavour from a few notable silicon designers, able to run Linux ‘well’ and adding a few novel security features that haven’t yet been put together this way before.

There are two interesting features that make the lowRISC notable. The first is tagged memory. This has been used before in older, weirder computers as a sort of metadata for memory. Basically, a few bits of each memory address tag each memory address as executable/non-executable, serve as memory watchpoints, garbage collection, and a lock on every word. New instructions are added to the ISA, allowing these tags to be manipulated, watched, and monitored to prevent the most common single security problem: buffer overflows. It’s an extremely interesting application of tagged memory, and something that isn’t really found in a modern architecture.

The second neat feature of the lowRISC are the minions. These are programmable devices tied to the processor’s I/O that work a lot like a Zynq SOC or the PRU inside the BeagleBone. Basically, they’re used for programmable I/O, implementing SPI/I2C/I2S/SDIO in software, offloading work from the main core, and devices that require very precise timing.

The current goal of the lowRISC team is to develop the hardware on an FPGA, releasing some beta silicon in a year’s time. The first complete chip will be an embedded SOC, hopefully release sometime around late 2016 or early 2017. The ultimate goal is an SOC with a GPU that would be used in mobile phones, set-top boxes, and Raspi and BeagleBone-like dev boards. There are enough people on the team, including [Robert Mullins] and [Alex Bradbury] of the University of Cambridge and the Raspberry Pi, researchers at UC Berkeley, and [Bunnie Huang].

It’s a project still in its infancy, but the features these people are going after are very interesting, and something that just isn’t being done with other platforms.

[Alex Bardbury] gave a talk on lowRISC at ORConf last October. You can check out the presentation here.